Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2001-12-05
2002-11-05
Nelms, David (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185280, C365S185180
Reexamination Certificate
active
06477088
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention is related to semiconductor memories and in particular to a method of erasing nonvolatile memories.
2. Description of Related Art
Metal Oxide Nitride Oxide Semiconductor (MONOS) memories have been proposed for improving the scaling down of devices, improving reproducibility of such devices as Metal Oxide Nitride Semiconductor (MNOS), and at the same time provide a low voltage alterable device. In the MONOS devices used in nonvolatile memory cells, carrier trap sites that are located in the nitride film are used for capturing and storing carriers as electrical information.
A paper, E. Suzuki et al., “A Low Voltage Alterable EEPROM with Metal Oxide Nitride Oxide Semiconductor (MNOS) Structures”, IEEE Transactions on Electron Devices, Vol. ED-30, No. 2, February 1983, p122-128, is directed to the use of direct tunnel injection of electrons into trap sites for write and erase of the electrons in the trap sites. The paper, Y. Tarui et al., “Electrically Reprogrammable Nonvolatile Semiconductor Memory”, IEEE Journal of Solid State Circuits, Vol, SC-7, No. 5, October 1992, p369-375, is directed to programming single gate MONOS memories with thicker bottom oxide for better retention characteristics. In T. Y. Chan et al., “A True Single Transistor Oxide Nitride Oxide EEPROM Device”, IEEE Electron Device Letters, Vol. EDL-8, No. 3, March 1987, p93-95, a single transistor device is directed toward storing electrons in the short region near the drain, wherein the channel near the source maintains the original threshold voltage, thereby eliminating the need for a select transistor. In B. Eitan et al., “Can NROM, a 2 Bit, Trapping Storage NVM Cell, Give a Real Challenge to Floating Gate Cells”, Extended Abstracts, 1999 Conference on Solid State Devices and Materials, Tokyo, 1999, P522-524, an NROM concept is directed to store charge selectively in an ONO dielectric on one side of a diffusion edge, and to erase by hole injection, which is generated by band-to-band tunneling at the junction edge. A twin MONOS device structure separating ONO storage devices by a select (word) gate device while maintaining high density is given in U.S. Pat. No. 6,255,166 B1 and U.S. patent application Ser. No. 09/595,059. In the patent application Ser. No. 09/795,186, dated Mar. 1, 2001 and assigned to a common assignee, two erase methods of hole injection and F-N electron ejection are provided.
In prior art, erase is achieved by electron ejection from the ONO nitride trap sites or by hole injection into the electron trap sites, or by a combination of the two mechanisms. Hot hole injection begins when holes are created at the junction's edge, between the high voltage diffusion region and the grounded substrate. The holes then inject into the memory nitride and cancel out the trapped electron charge. Hole injection requires lower voltages than the conventional Fowler-Nordheim tunneling electron ejection. However hole injection is primarily localized to the region above the junction edge, and can not erase the entire length of the electron-trapped nitride layer. This is why prior art required a combination of hole injection and electron ejection (by F-N tunneling) for effective erase. However, the twin MONOS device of the prior art has a very short control gate memory channel length.
FIG. 1
shows a twin MONOS cell structure of prior art in which there are two N+ bit diffusion
41
&
42
, above which are are two control gates
61
and
62
, between which is a word gate
63
. The substrate
20
is p-type, and nitride trap layers
51
t
&
52
t
store electrons for storage underneath the control gates
61
and
62
. In the twin MONOS cell shown in
FIG. 1
, Erase is done by hole injection using band to band generation. Electrons trapped in the ONO trap sites of
51
t
and
52
t
are neutralized by injected holes, which were generated by Band to Band tunneling at N+ junction edge
41
and
42
. The bias conditions are typically Vb=+4 to +5V on bit N+ diffusions
41
and
42
and Vcg=−1 to −3 volts on control gate
61
and
62
while word gate
63
is grounded as shown in
FIG. 2
a
. The voltage requirement for hole injection across the ONO film needs to be only about 5-6 megavolts/cm. However, the threshold window is adversely affected because the heavier holes cause more damage to the oxide-insulator than electrons and create trapping sites after many program and erase cycles.
Hole injection can be reduced by reducing Band to Band hot hole generation. When the same positive potential is applied to the p substrate
20
, Vb=Vsub=+4 to +5 volts as shown in
FIG. 2
b
, as applied to the bit N+ diffusion
41
and
42
, the hole generation due to band to band tunneling is suppressed. Once the potential between the substrate and the control gate voltage becomes high enough (>8-10 megavolts/cm), electrons from trapped sites (
51
t
and
52
t
) are ejected into silicon
31
and
32
by means of Fowler-Nordheim (FN) tunneling. However this FN erase approach requires a triple well (p-well in an n-well on a p-substrate) to isolate each memory cell block from supporting devices during positive voltage biasing of the well. Since the triple well must be deep, the triple well isolation for each block results in significant density penalty.
In these methods, erase is determined by the control gate and bit diffusion voltages. In the cases that the memory cells are arranged such that control lines and bit lines run parallel to each other, it is necessary to divide the array either electrically by select transistors or physically with separate lines in order to define the erase block size. This array division could impact density.
SUMMARY OF THE INVENTION
It is an objective of the present invention to enhance erase speed or lower the erase voltage requirement in the twin MONOS cell, by changing the distribution of high energy holes, which are created at the junction edge under the memory control gate, through the application of a negative voltage on the word gate adjacent to the selected memory control gate.
It is also an objective of the present invention to reduce erase speed in the scaled twin MONOS cell by depleting holes under the memory control gate towards the substrate through the application of a positive voltage onto the word gate adjacent to the selected memory control gate.
It is another objective of the present invention to erase by word line in the memory array, instead of by large block size, by applying a negative voltage on the selected word gate.
It is a further objective of the present invention to inhibit erase of the cell in normal erase conditions by providing a positive word channel potential adjacent to the memory channel under the control gate by applying a positive potential to the word gate, the opposite control gate and opposite control gate diffusion.
It is yet another objective of the present invention to achieve a one cell erase (or a two cell erase) in the memory array through the selection of word gate, control gate and bit diffusion voltages.
It is also another objective of the present invention to reduce hole injection for high endurance by a F-N like erase mechanism through a positive word gate voltage, a positive word channel potential, and selecting proper word gate, control gate and bit diffusions.
It is a further objective of the present invention to use negative voltage on unselected word lines to minimize disturb during programming.
The first embodiment of the present invention provides a method to control the erase speed over a range of greater than 5 orders of magnitude by application of positive and negative voltages onto the word gate of a twin MONOS memory device where the control gate channel length of about less than 50 nm, is less than several times the hole mean free path. The twin MONOS memory cell has an extremely short control gate channel length of less than several times the electron and hole mean free path length. This
Ogura Seiki
Ogura Tomoko
Saito Tomoya
Ackerman Stephen B
Halo LSI Design & Device Technology, Inc.
Lam David
Nelms David
Saile George O.
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