Upscaled clock feeds memory to make parallel waves

Details Upscaled clock feeds memory to make parallel waves Upscaled clock feeds memory to make parallel waves

2001-10-03

2003-10-21

Lam, Tuan T. (Department: 2829)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Clock or pulse waveform generating

C327S291000, C327S296000

Reexamination Certificate

active

06636096

ABSTRACT:

BACKGROUND OF THE INVENTION
The invention relates to an integrated circuit as recited in the preamble of claim 1. Today's integrated circuits, and in particular those for use in telecom applications are provided with a plurality of different clock domains that each run at different dedicated high frequencies. This is done in particular for power saving reasons. As an underlying condition, the clock input for the overall device should be in a relatively low frequency range. Requirements to the various circuitry clocks will often change repeatedly during the design process, which then will cause appreciable delay to the commercial introduction of such circuits. Earlier designs have encompassed a power-consuming full-featured block solution, which especially for portable and battery-powered standalone applications is unattractive for users.
SUMMARY TO THE INVENTION
In consequence, amongst other things, it is an object of the present invention to allow driving the various application utility circuitry functions at their respective optimum reconfigured clock signals whilst making these latter clock signals programmable until at a late stage of the design process, wilst furthermore requiring no more than a low-frequency primary clock frequency source. Now therefore, according to one of its aspects the invention is characterized according to the characterizing part of claim 1. Inter alia, it has been found that power consumption may be reduced by a factor of 5-10.
A further object of the present invention is to allow reconfigured clock signals that have wave-shape patterns defined for various different duty cycles and/or non-standard wave shapes. A still further object of the present invention is to improve testability, which improvement is attained indeed through the overall reduced functionality of the clock generation block.
Further advantageous aspects of the invention are recited in dependent claims.


REFERENCES:
patent: 4122309 (1978-10-01), Jacobsen
patent: 4306190 (1981-12-01), Beckwith et al.
patent: 4553100 (1985-11-01), Nishiura
patent: 4855681 (1989-08-01), Millham
patent: 5517147 (1996-05-01), Burroughs et al.
patent: 5583450 (1996-12-01), Trimberger et al.
Yamaguchi et al: “A new timing generator IC for a CCD imager” IEEE 1988 International Conference On Consumer Electronics (ICCE), pp. 56-57.

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