Upper medium access control processor architecture

Details Upper medium access control processor architecture Upper medium access control processor architecture

1997-07-31

2000-04-18

Tsang, Fan S.

Telecommunications

Radiotelephone system

Programming control

455515, 455422, 455560, 455466, 370336, 370329, 39520053, 39520054, H04J 316

Patent

active

060525800

ABSTRACT:
A upper medium access control processor is functionally defined by a set of tasks, where each task has a linked list queue for holding messages. Communications between tasks are achieved by placing the message onto the linked list queue of the desired task. The tasks are arranged into a plurality of prioritized groups for execution. The scheduler utilizes a N-phase scheme where tasks in a specific set of groups are executed at each phase. All tasks are guaranteed to run at least once during a complete cycle, thus preventing task starvation. The scheduler accommodates both synchronous and asynchronous tasks and still maintains the given priority scheme.

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patent: 5734645 (1998-03-01), Raith et al.
patent: 5796951 (1998-08-01), Hamner et al.
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patent: 5842210 (1998-11-01), Chen et al.
patent: 5875343 (1999-02-01), Binford et al.

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