Electrical pulse counters – pulse dividers – or shift registers: c – Systems – Using particular code or particular counting sequence
Reexamination Certificate
2001-12-07
2003-10-28
Wambach, Margaret R. (Department: 2816)
Electrical pulse counters, pulse dividers, or shift registers: c
Systems
Using particular code or particular counting sequence
C377S045000, C377S114000, C250S208100, C250S234000, C250S235000
Reexamination Certificate
active
06639963
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a Gray code counter, and relates particularly to an up/down Gray code counter that can count both up and down.
2. Description of the Prior Art
Conventional counters are binary code counters that use a binary code as shown in FIG.
3
. In
FIG. 3
is shown a binary code of which each codeword consists of five bits. In a binary code counter, when the count as represented in decimal notation increases by one, a plurality of bits may change simultaneously. For example, when the count in decimal notation changes from “0” to “1,” the binary codeword changes from “00000” to “00001,” and thus only one bit changes; by contrast, when the count in decimal notation changes from “15” to “16,” the binary codeword changes from “01111” to “10000,” and thus five bits change simultaneously. The larger the number of bits that change simultaneously, the more the electric current consumed to achieve the change, and this produces electric noise. Such electric noise may lead to interference among the signals within the counter, and thus to malfunctioning of the whole system.
As a counter with reduced electric noise resulting from simultaneous change of a plurality of bits as described above, Gray code counters that use a Gray code as shown in
FIG. 3
have been proposed. In
FIG. 3
is shown a Gray code of which each codeword consists of five bits. In a Gray code, two consecutive counts in decimal notation differ only in one bit and are identical in the other bits. That is, between any two consecutive counts in decimal notation, only one bit changes. As a result, a Gray code counter requires less electric current to achieve bit change than a binary code counter, and thus can reduce electric noise resulting from simultaneous change of a plurality of bits.
On the other hand, some solid-state image sensors employ a decoder-type scanning circuit. A decoder-type scanning circuit scans the address that coincides with the value output from a counter. In a solid-state image sensor, scanning from the address having the smallest value upward results in a normal image mode, and scanning from the address having the greatest value downward results in a mirror image mode. Therefore, to operate a solid-state image sensor both in a normal image mode and in a mirror image mode, it is necessary to use a counter that can count both up and down.
A typical example of the logic circuit used in a conventional up/down Gray code counter that operates with reduced electric noise and that can count both up and down is shown in FIG.
6
. In
FIG. 6
is shown a conventional up/down Gray code counter of a five-bit type. The conventional up/down Gray code counter
10
is provided with an up count clock generating circuit
11
and a down count clock generating circuit
12
. According to a command signal MIR, a clock switching circuit
13
chooses between the signal output from the up count clock generating circuit
11
or the signal output from the down count clock generating circuit
12
, and feeds the chosen signal to flip-flops FF
11
to FF
15
. Specifically, the clock switching circuit
13
outputs, for up counting, the signal from the up count clock generating circuit
11
and, for down counting, the signal from the down count clock generating circuit
12
.
Examples of up/down Gray code counters provided with a logic circuit section for up counting and a logic circuit section for down counting include not only the up/down Gray code counter shown in
FIG. 6
but also the up/down Gray code counter disclosed in Japanese Patent Application Laid-Open No. H1-251822.
The conventional up/down Gray code counter described above is provided with both a logic circuit section for up counting and a logic circuit section for down counting. Disadvantageously, this configuration requires additional provision of a logic circuit section that operates in down counting, which is not found in a Gray code counter that only counts up, a and thus requires a larger circuit scale.
SUMMARY OF THE INVENTION
An object of the present invention is to provide an up/down Gray code counter with a smaller circuit scale. Another object of the present invention is to provide a solid-state image sensor that is switchable between a normal image mode and a mirror image mode but that is nevertheless ready to be miniaturized.
To achieve the above objects, according to one aspect of the present invention, an up/down Gray code counter is provided with a one-way Gray code counter that can count only in one, up or down, direction and a highest bit selecting circuit that receives the highest bit of the data output from the one-way Gray code counter and that then outputs the bit selectively either intact or after inverting it.
According to another aspect of the present invention, a solid-state image sensor is provided with a plurality of photoelectric conversion elements and a scanning circuit including an up/down Gray code counter for sequentially reading signals from the photoelectric conversion elements. Here, the up/down Gray code counter is provided with a one-way Gray code counter that can count only in one, up or down, direction and a highest bit selecting circuit that receives the highest bit of the data output from the one-way Gray code counter and that then outputs the bit selectively either intact or after inverting it.
REFERENCES:
patent: 4937845 (1990-06-01), Warner
patent: 5191425 (1993-03-01), Hachiyama et al.
patent: 69130780 (1999-06-01), None
patent: 0459248 (1991-12-01), None
patent: 0691744 (1996-01-01), None
patent: A1-251822 (1989-10-01), None
patent: 02261275 (1990-10-01), None
Sharp Kabushiki Kaisha
Wambach Margaret R.
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