Up/down counter device with reduced number of discrete circuit e

Details Up/down counter device with reduced number of discrete circuit e Up/down counter device with reduced number of discrete circuit e

1985-07-12

1988-04-26

Miller, Stanley D.

Electrical pulse counters, pulse dividers, or shift registers: c

Pulse counting or dividing chains

Ring or reversible counter

377115, 377116, 3072721, H03K 2300, H03K 2304

Patent

active

047410060

ABSTRACT:
An up/down counter device includes a D-type flip-flop circuit for producing a count signal of the 0th bit in synchronism with a clock signal, and 1st to n-th flip-flop circuits for producing count signals of the 1st to the n-th bits in synchronism with a clock signal. The first logic circuit is connected between the output of the D-type flip-flop circuit and the JK terminals of the first flip-flop circuit. The first stage logic circuit includes a first logic circuit section supplied with an up/down mode signal and the output signal of the D-type flip-flop circuit, and a second logic circuit connected in series with with the first logic circuit. Each of the 2nd to the n-th stage logic circuits includes a first logic circuit which is connected between the output terminal of the prestage flip-flop circuit and the JK terminals of the post stage flip-flop circuit, and a second logic circuit section connected to the first logic circuit. The output of the first logic circuit section of each of the first to the n-th logic circuits is connected to the input of the first logic circuit section of the post stage logic circuit.

REFERENCES:
patent: 3277380 (1966-10-01), Paufve
patent: 3500022 (1970-03-01), Toscano
patent: 3588475 (1971-06-01), Scott
patent: 3614580 (1971-10-01), Eto
patent: 3632997 (1972-01-01), Froemke
patent: 3671875 (1972-06-01), Pento
patent: 4037085 (1977-07-01), Minorikawa
patent: 4378505 (1983-03-01), Scavuzzo
Toshiba, "Semiconductor Circuit Technique Data", C2MOS (Separate Standard) Fifth Edition pp. 275-279, Aug. 1982.

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