Electrical pulse counters – pulse dividers – or shift registers: c – Systems – With programmable counter
Patent
1983-11-29
1986-05-27
Miller, Stanley D.
Electrical pulse counters, pulse dividers, or shift registers: c
Systems
With programmable counter
377 45, 377 54, G06M 300
Patent
active
045920788
DESCRIPTION:
BRIEF SUMMARY
DESCRIPTION
1. Technical Field
The present invention relates to an up/down counter control circuit suitable for use with a phase locked loop synthesizer receiver.
1. Background Art
In the art, an up/down counter has been used to vary the frequency dividing ratio of a programmable divider used in a phase locked loop.
As a control circuit for the up/down counter of such kind, there is proposed the circuit, for example, shown in FIG. 1. In FIG. 1, reference numeral 1 designates an input terminal to which an up/down counter control signal is supplied, 2 an up/down counter controller, 3 an up/down counter, 4 an input terminal to which an up/down clock signal is supplied, 5 a shift register, 6 an input terminal to which a latch clock signal is supplied, 7 an AND gate circuit, 8 an input terminal to which a serial data signal is supplied, and 9 an input terminal to which a shift clock signal is supplied.
In the normal mode, the serial data from the input terminal 8 is inputted to the shift register 5 in synchronism with the clock signal supplied from the input terminal 9. The serial data is also latched in the up/down counter 3 in response to the clock signal from the input terminal 6. In the up/down mode, when an up/down signal Sa to be supplied to the input terminal 1 changes from "0" to "1" as shown in FIG. 2A, the content in the up/down counter 3 is transferred to the shift register 5 when a signal Sb from the up/down controller 2 shown in FIG. 2B occurs. Also, at the same time when the up/down counter 3 is set to the up mode in response to a signal Sd, which is shown in FIG. 2D, supplied from the up/down controller 2, the AND gate circuit 7 is opened in response to a signal Sc, which is shown in FIG. 2C, supplied from the up/down controller 2 so that in response to the output from the AND circuit 7 the content in the shift register 5 is returned to the up/down counter 3. After that subsequently, an up/down clock signal Se, which is shown in FIG. 2E, is supplied from the input terminal 4 to the up/down counter 3 and hence the content thereof is changed to the UP direction.
In the case of the conventional circuit shown in FIG. 1, in order to transfer the serial data from a control circuit (not shown) such as a microprocessor and the like to the shift register 5, it is necessary to transfer the serial data signal, the shift clock signal and the latch clock signal. Furthermore, as the signals for controlling the above up/down counter 3, the up/down clock signal and the up/down control signal must be transferred, which requires a large number of control lines.
DISCLOSURE OF INVENTION
Accordingly, it is a first object of the present invention to provide an up/down counter control circuit which can obviate the above defects.
It is another object of the present invention to provide an up/down counter control circuit which can reduce the number of control lines as much as possible.
According to an embodiment of the present invention, there is provided an up/down counter control circuit having a timing control means to which a latch signal, a data and a clock signal are supplied, a data memory means and an up/down counter wherein on the basis of the control by the timing control means, in the data latch mode, the first level (0 or 1) of the latch signal is detected and in synchronism with the latch signal the above data is latched in the data memory means, while in the up/down mode, the second level (1 or 0) of the latch signal is detected and the content of the up/down counter is changed in response to the level of the above data synchronized with the clock signal.
BRIEF DESCRIPTION OF DRAWINGS
FIG. 1 is a systematic diagram showing an example of a conventional circuit,
FIG. 2 is a diagram useful for explaining the operation of FIG. 1,
FIG. 3 is a systematic diagram showing an embodiment of the present invention,
FIGS. 4 to 7 are diagrams useful for explaining the operation of FIG. 3,
FIG. 8 is a circuit diagram showing an example of a main part of the present invention,
FIG. 9 is a connection diagram showing
REFERENCES:
patent: 3701106 (1972-10-01), Loshbough
Miller Stanley D.
Ohralik K.
Sony Corporation
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