Unmolded package for a semiconductor device

Details Unmolded package for a semiconductor device Unmolded package for a semiconductor device

2002-09-04

2004-05-25

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Assembly of plural semiconductive substrates each possessing...

C438S106000, C438S612000, C438S613000

Reexamination Certificate

active

06740541

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a package for a semiconductor device, and more particularly, to a package for a semiconductor device that does not require a molded body.
2. Description of the Prior Art
Semiconductor devices, especially MOSFET devices, generally desire very low package resistance (RDSon) with good thermal performance. It is also generally desirable to have simple, quick and efficient methods of packaging semiconductor devices. Thus, numerous packaging concepts and methods have been developed in the prior art.
An example of one such packaging concept involves a ball grid array (BGA). Such a concept involves an array of source, gate and drain solder balls that are connected directly to the printed circuit board (PCB). This requires a bumped die and a leadframe is used to facilitate the drain contact. Another packaging concept is commonly referred to as Flip Chip in Leaded Molded Package (FLMP), which comprises a molded leaded surface mount package where a bumped die is connected to gate and source terminals of the frame. The drain, which is the back side of the die, is exposed from the mold compound or body and is connected to the PCB via solder reflow during a standard board mounting process. Other packaging concepts use copper straps and/or wire bond technology.
These prior art concepts involve various components and may result in complicated manufacturing (packaging) processes.
SUMMARY OF THE INVENTION
The present invention provides a semiconductor device that includes a substrate and a die coupled to the substrate. Multiple solder balls are also coupled to the substrate adjacent to the die. The solder balls are substantially coplanar with a surface of the die when the semiconductor device is coupled to a printed circuit board. Thus, when the semiconductor device is coupled to a PCB, the surface of the die not coupled to the substrate serves as a direct drain connection while the substrate and solder balls serve as the source and gate connections in the instance when the semiconductor device is a MOSFET device.
In accordance with one aspect of the present invention, the substrate includes a base layer, a metal layer and an insulating layer between the base layer and the metal layer.
In accordance with another aspect of the present invention, the base layer comprises a metallized pattern and the metal layer comprises another metallized pattern or serves as a heat spreader.
In accordance with a further aspect of the present invention, the substrate is a metallized ceramic.
In accordance with yet another aspect of the present invention, the substrate comprises two layers of metallized ceramic which can facilitate attachment of two dies (silicon) on opposite faces.
The present invention also provides a method of packaging a semiconductor device that includes providing a substrate and a die. The solder, or any suitable electrically conductive interconnect in the case of MOSFET devices, is placed on at least one of the substrate and the die and the die is flipped onto the substrate. The solder balls are then placed on the substrate adjacent to the die.
Other features and advantages of the present will be understood and upon reading and understanding the detailed description of the preferred exemplary embodiments found hereinbelow, in conjunction with reference to the drawings, in which like numerals represent like elements.


REFERENCES:
patent: 5616958 (1997-04-01), Laine et al.
patent: 5777386 (1998-07-01), Higashi et al.
patent: 6049624 (2000-04-01), Wilson et al.
patent: 6137164 (2000-10-01), Yew et al.
patent: 6168973 (2001-01-01), Hubbard
patent: 6225699 (2001-05-01), Ference et al.
patent: 6462421 (2002-10-01), Hsu et al.
patent: 6479903 (2002-11-01), Briar

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