Unlimited phase tracking delay locked loop

Details Unlimited phase tracking delay locked loop Unlimited phase tracking delay locked loop

1999-09-30

2001-03-20

Ton, My-Trang Nu (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Phase shift by less than period of input

C327S156000

Reexamination Certificate

active

06204709

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates to a method and apparatus for enabling unlimited phase tracking in high speed data synchronisation, for example in telecommunications equipment. The invention relates in particular to a delay locked loop which provides continuous, precise alignment of two signals in excess of one signal period. The invention also relates to a phase shifter circuit which provides phase shifting over more than one signal period.
With increasingly higher data rates becoming common place, particularly in optical systems, it is becoming increasingly difficult to guarantee clock and data alignment. Variations in integrated circuit parameters and printed circuit board signal delays leave a very small time in which clock and data signals may be aligned. These signal delays vary with production tolerances and operating temperatures which can cause significant design problems at high data rates. Frequency and phase locked loops are often used to manage the clock and data alignment and to maintain data integrity throughout the operating range of the high speed data equipment. A delay locked loop, which is a type of phase locked loop, uses a phase detector to generate an error voltage proportional to the phase difference between two input signals. The error voltage is, in turn used to control a phase shifter which adjusts the delay, or phase, of one of the signals to achieve phase alignment of the two signals. Such a circuit allows the phase changes of either signal to be continuously and precisely tracked. The circuit is limited to tracking changes of less than one signal period, that is phase differences in excess of ±180° may not be accurately tracked by the phase shifter and can cause the loop to become unstable.
One accepted method of overcoming this instability is to detect the limit of the phase difference and to recentre the phase shifter. Since it is not possible to maintain signal alignment whilst the phase shifter, and thus the loop, is being reset, this results in a temporary loss of alignment. As a consequence, such circuits are unsuitable for use in high speed data equipment where the temporary loss of alignment can severely affect the data integrity of several kilobytes of data.
An alternative approach may be to operate the loop at a submultiple frequency of the signals being tracked. The disadvantage of this approach is that the original frequency needs to be recovered before the output signals can be used. This process introduces further errors and complications into the circuitry.
There is thus a need for an improved phase shifter and delay locked loop which do not suffer from the disadvantages outlined above.
It is an object of the invention to provide a phase shifter which can track phase changes seamlessly, which maintains alignment throughout all phase differences and which does not introduce further complexity or errors.
SUMMARY OF THE INVENTION
According to a first aspect of the invention there is provided a phase shifter reset circuit, for phase shifting an input signal, having an input and an output, comprising:
a phase shifter, having a first input for receiving said input signal, a second input for receiving a phase shift reference signal and an output for outputting a phase shifted input signal, wherein the phase of the input signal is shifted by a phase shifter determined by the phase shift reference signal;
a resetter, for resetting the phase shift reference signal in response to a trigger signal;
a fixed phase shifter, for shifting the phase of said input signal by a predetermined phase shift, connected in parallel with said phase shifter, having an input for receiving said input signal and an output for outputting a fixed phase shifted input signal;
a threshold detector circuit, having an input for receiving said phase shift reference signal and an output for outputting a switching signal when said phase shift reference signal reaches a threshold level, substantially equivalent to the phase shift introduced into said input signal by the fixed phase shifter;
a bypass circuit, disposed between said phase shifters and said output, having two inputs for receiving, respectively, said phase shifted input signal and said fixed phase shifted signal, a switch for selecting a selected signal from either said phase shifted input signal or said fixed phase shifted signal, an output for outputting said selected signal and means for generating said trigger signal, whereby said switch is responsive to said switching signal to switch from said phase shifted input signal to said fixed phase shifted signal for a predetermined period of time, during which time said trigger signal is generated, before switching back to said phase shifted input signal.
According to a second aspect of the invention there is provided a method of resetting a phase shifter to provide a continuously phase shifted output signal comprising:
phase shifting, in a phase shifter, said input signal by a phase shift determined by a phase shift reference signal to produce a phase shifted input signal;
resetting said phase shifter in response to a trigger signal;
phase shifting, in a fixed phase shifter disposed in parallel with said phase shifter, said input signal by a predetermined phase shift to produce a fixed phase shifted input signal;
detecting in a threshold detector when said phase shift reference signal reaches a predetermined threshold, equivalent to the phase shift introduced by said fixed phase shifter and generating in response a switching signal;
switching at said output, in response to said switching signal, from said phase shifted input signal to said fixed phase shifted input signal for a predetermined period of time, during which time said trigger signal is generated, before switching back to said phase shifted input signal.
According to a third aspect of the invention there is provided a first input for receiving an input signal, a delay locked loop, having an output for generating an output signal and a second input for receiving a delayed version of output signal, for inserting a delay representative of the delay inserted into the output signal into the output signal comprising:
a phase detector, having a first input for receiving said input signal and a second input for receiving said delayed version of the output signal, for generating and outputting at an output a phase shift reference signal representative of the phase difference between said input signal and said delayed version of the output signal;
a phase shifter, having a first input for receiving said input signal, a second input for receiving said phase shift reference signal and an output for outputting a phase shifted input signal, wherein the phase of the input signal is shifted by a phase shift determined by the phase shift reference signal;
a resetter, for resetting the phase shift reference signal in response to a trigger signal;
a fixed phase shifter, for shifting the phase of said input signal by a predetermined phase shift, connected in parallel with said phase shifter, having an input for receiving said input signal and an output for outputting a fixed phase shifted input signal;
a threshold detector circuit, having an input for receiving said phase shift reference signal and an output for outputting a switching signal when said phase shift reference signal reaches a threshold level, substantially equivalent to the phase shift introduced into said input signal by the fixed phase shifter;
a bypass circuit, disposed between said phase shifters and said output, having two inputs for receiving, respectively, said phase shifted input signal and said fixed phase shifted signal, a switch for selecting a selected signal from either said phase shifted input signal or said fixed phase shifted signal, an output for outputting said selected signal and means for generating said trigger signal, whereby said switch is responsive to said switching signal to switch from said phase shifted input signal to said fixed phase shifted signal for a predetermined period of time, during which time s

Affiliated with

Also associated with

Rating

Unlimited phase tracking delay locked loop does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Unlimited phase tracking delay locked loop, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Unlimited phase tracking delay locked loop will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2501175