Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
1999-05-26
2002-04-02
Loke, Steven (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S760000, C257S759000, C257S762000
Reexamination Certificate
active
06365971
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to semiconductor processing. More specifically, the present invention relates to a structure and method for forming an unlanded via.
2. Description of Related Art
During manufacturing of a semiconductor integrated circuit, electrically conductive materials patterned in electrical circuitry are layered over a base transistor structure that is disposed on a semiconductor substrate. The electrically conductive materials, such as copper, are in different and noncontiguous planes. Vias or pathways connect the various layers of electrically conductive materials. An insulator or a dielectric material is placed between the separate planes of conductive material around the vias and also within the trenches and the circuit pattern of a layer of conductive material. Vias are usually formed as landed vias, which rest entirely on a conductive layer, and not as unlanded vias, which rest partially on a conductive layer and partially on an insulator.
The demand for closer packing of devices means increased packing density of vias. Unlanded vias are preferable to landed vias in order to achieve a higher packing density. In addition, because better device performance can be achieved with lower capacitance between conductive lines within an insulating layer, the industry is moving toward using insulators with a lower dielectric constant (K), such as an organic polymer (K~2.5) instead of silicon dioxide (K~4.0). Thus, the next generation of chip sets requires unlanded vias and low dielectric constant materials as intraline dielectrics.
FIG. 1
is a cross-section illustrating an interconnect structure in which two landed vias
111
and
113
are formed according to a prior art method. Metal lines
100
with oxide caps
103
are patterned and formed. A polymer
105
is then deposited and filled around the metal lines
100
. Polymer
105
is polished back using chemical-mechanical polish until a top surface of polymer
105
is flush with a top surface of oxide cap
103
. A thin passivation layer
107
is then deposited. Next, an interlayer dielectric
109
, such as silicon dioxide, is deposited. Standard lithography is used to form landed vias
111
and
113
. Landed vias
111
and
113
are created by etching through interlayer dielectric
109
, through passivation layer
107
, and through oxide cap
103
until landed vias
111
and
113
contact metal lines
100
.
The same process is then used to create unlanded vias
200
and
202
in FIG.
2
. Unfortunately, the prior art method shown in
FIG. 1
cannot be used to create unlanded vias
200
and
202
. During the etch of unlanded vias
200
and
202
, polymer
105
has been punched through, which leads to device reliability problems. In addition, unlanded vias
200
and
202
cannot be filled with a metal, such as tungsten, because tungsten cannot nucleate on a polymer
105
. Thus, a void is created and device performance is degraded. Thus, the prior art method cannot be used to create unlanded vias
200
and
202
as shown in
FIG. 2
in the presence of a polymer. Therefore, the prior art method fails to allow the fabrication of unlanded vias over a metal and a polymer that is used as an intraline dielectric.
SUMMARY
The present invention relates to a method for forming an interconnect structure. The method comprises the following steps. A conductive structure having an insulator cap is formed. A low dielectric constant material is formed over the conductive structure. The low dielectric constant material is planarized. The low dielectric constant material is then selectively removed to create a recess. A stop layer is formed over the recess of the low dielectric constant material and over the conductive structure. The stop layer is then planarized.
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patent: 5312512 (1994-05-01), Allman et al.
patent: 5599740 (1997-02-01), Jang et al.
patent: 5721157 (1998-02-01), Sunada
patent: 5750415 (1998-05-01), Gnade et al.
patent: 5789818 (1998-08-01), Havemann
patent: 5804503 (1998-09-01), Leidy et al.
patent: 5851916 (1998-12-01), Howard
patent: 5864880 (1998-12-01), Lee
patent: 5926732 (1999-07-01), Matsuura
Chen George
Intel Corporation
Loke Steven
Owens Douglas W.
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