Universal weight generator

Excavating

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Details

364717, G01R 3128

Patent

active

053944054

ABSTRACT:
A cascaded arrangement of alternating AND gates and Exclusive-OR gates is employed in conjunction with an output from a pseudo-random signal generator to produce a weighted random pattern binary sequence which is granularly controllable in terms of user selected probabilities and for which the granularity level is readily controlled through the selection of a desirable number of cascaded stages.

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patent: 5239262 (1993-08-01), Grutzner et al.
A Method for Generating Weighted Random Test Patterns by J. A. Waicukauski et al., IBM Journal of Research and Development, vol. 33, No. 2, Mar. 1989, p. 149.
Cellular Automata Circuits for Built-In Self-Test by P. D. Hortensius et al, IBM Journal of Research and Development, vol. 34 No. 2/3, Mar./May 1990 p. 389.
Multiple Distributions for Biased Random Test Patterns by H. Wunderlich, IEEE Transactions on Computer-Aided Design, vol. 9, No. 6, Jun. 1990, p. 584.
The Weighted Random Test-Pattern Generator by H. D. Schnurmann et al., IEEE Transactions on Computers, vol. C-24, No. 7, Jul. 1975, p. 695.
Hardware-Based Weighted Random Pattern Generation for Boundary Scan by F. Brglez et al., IEEE, Paper 13.3, 1989, p. 264.
Interfacing to Boundary Scan Chips for System Level Bit by J. Turino, IEEE, 1989, p. 310.
Random Pattern Testing of LSSD Logic Devices by Multiple Sets of Weights by E. B. Eichelberger et al., IBM Technical Disclosure Bulletin, vol. 31, No. 8, Jan. 1989, p. 467.
Fixed-Bias an Variable-Bias Random Pattern Generator by A. L. Herman, IBM Technical Disclosure Bulletin, vol. 27, No. 1B, p. 468.
Weight Random Pattern Geenration for Self-Test by M. C. Noecker, IBM Technical Disclosure Bulletin, vol. 32, No. 10A, Mar. 1990, p. 140.

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