Universal test platform and test method for latch-up

Details Universal test platform and test method for latch-up Universal test platform and test method for latch-up

2006-08-08

2006-08-08

Hoff, Marc S. (Department: 2857)

Data processing: measuring, calibrating, or testing

Testing system

Of circuit

C324S765010

Reexamination Certificate

active

07089137

ABSTRACT:
A method for testing latch-up phenomenon of a chip is provided. The chip is tested on a test platform, the test platform storing a test program of the chip for testing the chip. The method includes (a) obtaining the test program of the chip tested on the test platform, (b) obtaining pin data of the chip by the test program of the chip, (c) setting up an input pin of the chip with an initial value, and (d) providing a test current to the pin of the chip, and then measuring the current between a power end and a ground end of the chip to see if it exceeds a first predetermined value.

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patent: 6028438 (2000-02-01), Gillette
patent: 6393593 (2002-05-01), Tsujii
patent: 6429676 (2002-08-01), Chun et al.
patent: 6586921 (2003-07-01), Sunter
patent: 6940271 (2005-09-01), West

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