Universal pulse width modulating power converter

Details Universal pulse width modulating power converter Universal pulse width modulating power converter

2001-10-04

2002-10-22

Nguyen, Matthew (Department: 2838)

Electric power conversion systems

Current conversion

Including d.c.-a.c.-d.c. converter

Reexamination Certificate

active

06469914

ABSTRACT:

FIELD OF THE INVENTION
The invention relates to the field of switching electrical power converters. More particularly, the invention relates to the field of pulse width modulating forward converters and post regulators.
BACKGROUND OF THE INVENTION
FIG. 1
illustrates a schematic block diagram of a conventional pulse width modulating (PWM) forward converter. As illustrated in
FIG. 1
, a voltage source V
S
is coupled to a first terminal of a primary winding of a transformer T. A second terminal of the primary winding of the transformer T is coupled to a drain of a MOS transistor M. A source of the transistor M is coupled to a first terminal of a resistor R
SENSE
. A second terminal of the resistor R
SENSE
is coupled to a first ground node. A voltage signal I
SENSE
formed at the first terminal of the resistor R
SENSE
is representative of a level of current passing through the primary winding of the transformer T when the transistor M is active.
A first terminal of a secondary winding of the transformer T is coupled to an anode of a diode D. A cathode of the diode D is coupled to a first terminal of a capacitor C
1
, to an output node, and to a first terminal of a resistor R
1
. A second terminal of the secondary winding of the transformer T and a second terminal of the capacitor C
1
are coupled to a second ground node. A second terminal of the resistor R
1
is coupled to a first terminal of a resistor R
2
and to an inverting input of an error amplifier A. A second terminal of the resistor R
2
is coupled to the second ground node. The resistors R
1
and R
2
form a resistive divider for supplying the amplifier A with a signal which is proportional to an output voltage V
OUT
at the output node. The amplifier A can include optical elements so as to optically isolate the first ground node from the second ground node.
A non-inverting input of the amplifier A is coupled to a reference voltage V
REF
. The reference voltage V
REF
is representative of a desired level for the output voltage V
OUT
. An output of the amplifier A forms an error signal V
EA
and is coupled to a non-inverting input of a comparator CMP
1
. The error signal V
EA
is representative of a difference between the output voltage V
OUT
and a desired level for the output voltage. The first terminal of the resistor R
SENSE
is coupled to an inverting input of the comparator CMP
1
and to an inverting input of a comparator CMP
2
. An output of the comparator CMP
1
is coupled to a first input of a logic NAND gate U
1
. A current source is coupled to a first terminal of a capacitor C
2
and to a non-inverting input of the comparator CMP
2
. A second terminal of the capacitor C
2
is coupled to the first ground node. A voltage signal V
START
is formed at the first terminal of the capacitor C
2
.
An output of the comparator CMP
2
is coupled to a second input of the NAND gate U
1
. An output of the NAND gate U
1
is coupled to a set input S of a flip-flop U
2
. A reset input R of the flip-flop U
2
is coupled to receive a clock signal V
CLK
. An inverted output {overscore (Q)} of the flip-flop U
2
is coupled to a gate of the transistor M.
When the transistor M is active (turned on), current flows from the source V
S
and through the primary winding of the transformer T. This stores energy as an electromagnetic field associated with the primary winding of the transformer T. When the transistor M is inactive (turned off), the electromagnetic field collapses. By turning the transistor M on and off, energy is transferred to the secondary winding of the transformer T which induces a current to flow in the secondary winding. The current in the secondary winding of the transformer T is rectified by the diode D so as to form a voltage across the capacitor C
1
. A duty cycle utilized for operating the transistor M controls the level of the output voltage V
OUT
formed at the output node.
FIGS. 2
a-b
illustrate timing diagrams for the signals V
EA
, I
SENSE
and V
CLK
of the PWM forward converter illustrated in FIG.
1
. When the clock signal V
CLK
transitions from a logical low voltage to a logical high voltage, the output {overscore (Q)} of the flip-flop U
2
transitions to a logic high voltage. This turns on the transistor M. Under these conditions, current flows through the transistor M and the resistor R
SENSE
, as illustrated in
FIG. 2
a
by the signal I
SENSE
ramping up. When the signal I
SENSE
reaches the level of the error signal V
EA
, this causes the output of the comparator CMP
1
to change from a logic high voltage to a logic low voltage. As a result, the output of the NAND gate U
1
changes from a logic low voltage to a logic high voltage and the output {overscore (Q)} of the flip-flop U
2
transitions from. a logic high voltage to a logic low voltage. This turns off the transistor M. Upon a next transition of the clock signal V
CLK
, this cycle repeats. Note that as the error signal V
EA
increases, the transistor M stays on for a longer portion of each cycle of the clock signal V
CLK
because more time is required for the signal I
SENSE
to exceed the error signal V
EA
. Conversely, as the error signal V
EA
falls, the transistor M stays on a smaller portion of each cycle of the clock signal V
CLK
because less time is required for the error signal I
SENSE
to exceed the error signal V
EA
. Accordingly, the output voltage at the node V
OUT
is regulated to the desired level by adjusting the duty cycle of the transistor M according to requirements of a load (not shown) which can be coupled to the output node to receive the output voltage V
OUT
.
Under normal operating conditions, the voltage V
START
is at a higher level than the error signal V
EA
. Accordingly, the output of the comparator CMP
2
is a logic high voltage when the output of the comparator CMP
1
changes. Therefore, under normal operating conditions, the output of the comparator CMP
2
does not affect the duty cycle of the transistor M and the PWM converter operates as described above.
Upon start up, however, the output voltage V
OUT
is low. As a result, the error signal V
EA
is relatively large. In absence of soft-start circuit elements, including the current source I, the capacitor C
2
and the comparator CMP
2
, this large error signal would result in the transistor M being held on for a large portion of each cycle of the clock signal V
CLK
while the forward converter attempted to rapidly increase the output voltage to the desired level. As a result, excessive current would flow through the transistor M which would tend to cause premature failure of the transistor M.
Instead, upon start up, the current source I is turned on and the signal V
START
slowly ramps up. Before the level of the signal V
START
exceeds the level of the signal V
EA
, the duty cycle of the transistor M is not influenced by the signal V
EA
, but by the signal V
START
. As a result, the duty cycle of the transistor M gradually increases until the level of the signal V
START
exceeds the level of the error signal V
EA
.
While the soft-start circuit elements of
FIG. 1
provide a useful function, they also result in a disadvantage, especially when elements of the forward converter are incorporated into an integrated circuit. More particularly, so that the signal V
START
ramps up slowly, the current produced by the current source I must be small in relation to the size of the capacitor C
2
. This constraint either requires that the capacitor C
2
be external to the integrated circuit, which increases the pin count of the integrated circuit and, thus, the cost of producing the integrated circuit, or requires that the current produced by the current source I be so small as to be easily overwhelmed by noise and other transient signals, which reduces reliability.
Therefore, what is needed is improved soft-start technique for a PWM power converter.
Further, prior integrated circuits for controlling PWM power converters have been specifically tailored to the intended application. For example, a different integrated circuit design is utilized for a PWM forward convert

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