Universal output driver and filter

Details Universal output driver and filter Universal output driver and filter

1999-05-28

2000-09-05

Wong, Peter S.

Electricity: power supply or regulation systems

Output level responsive

Using a three or more terminal semiconductive device as the...

323315, 323313, G05F 140

Patent

active

06114844&

ABSTRACT:
An output driver is provided with driving and filtering capability. An output current driver and output voltage driver embodiments are provided. The output current driver includes, an operational amplifier having a first input for receiving a first input voltage V.sub.1, a second input for receiving a second input voltage V.sub.2, and an output for generating an output voltage Vc. The output current driver also includes a transistor having an input terminal coupled to the output of the operational amplifier for receiving the output voltage Vc, a first terminal coupled to a differential pair, and a second terminal coupled to the second input of the operational amplifier, wherein an output current I.sub.out flows across the transistor. A control current I.sub.CONTROL determines a value of the first input voltage V.sub.1, while the output voltage Vc controls the transistor so that the second voltage V.sub.2 becomes equal to the first voltage V.sub.1. The voltage driver includes, a first plurality of parallel modules coupled to an output load and capable of setting a first equivalent resistive value and a second equivalent resistive value, and a second plurality of parallel modules coupled to the output load and capable of setting a third equivalent resistive value and a fourth equivalent resistive value. At least some of the equivalent resistive values determine an output voltage value across the output load.

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patent: 5878082 (1999-03-01), Kishigami
Orsatti, Piazza, Huang, and Morimoto, "A 20 mA-receive 55 mA-transmit GSM transceiver in .25/spl mu/m CMOS", IEEE, pp. 232-233, Feb. 1999.
Johnson, Mark G, et al. "A Variable Delay Line PLL for CPU --Coprocessor Synchronization" Oct. 1988, pp. 1218-1223, IEEE Journal of Solid-State Circuits, vol. 23 No. 5.
Sonntag, Jeff, et al. "A Monolithic CMOS 10 MHz DPLL for Burst-Mode Data Retiming", Feb. 16, 1990, pp. 194-195 and 294, 1990 IEEE International Solid-State Circuits Conference Digest of Technical Papers, 37.sup.th ISSCC, First Edition.
Everitt, James, et al., "A CMOS Transceiver for 10-Mb/s and 100-Mb/s Ethernet", Dec. 1998, pp. 2169-2177, IEEE Journal of Solid-State Circuits, vol. 33, No. 12.

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