Universal input data sampling circuit and method thereof

Details Universal input data sampling circuit and method thereof Universal input data sampling circuit and method thereof

1996-12-10

1998-04-21

Clawson, Jr., Joseph E.

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

Having selection between plural continuous waveforms

327 24, 327 29, 327 30, 327298, 326 41, H03K 1992, H03K 1716

Patent

active

057421889

ABSTRACT:
A circuit for detecting timing errors and for selecting the correct clock edge for mid-point data sampling, includes a rising edge sampling device for sampling an input data signal at a rising edge of an input clock and generating a first interim data signal. A falling edge sampling device samples the input data signal at a falling edge of the input clock and generates a second interim data signal. An error signal generation devise, arranged in each of the rising edge and falling edge sampling devices, generates an error signal if designated setup time and hold time requirements are not met. The error signal is one of an error-rise or error-fall signal. A state machine receives the first and second interim signals and the error signal. The state machine automatically outputs the first interim data signal to a logic device if the error-fall signal is detected, and outputs the second interim data signal to the logic device if the error-rise signal is detected.

REFERENCES:
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patent: 5604452 (1997-02-01), Huang
patent: 5614845 (1997-03-01), Masleid
patent: 5623223 (1997-04-01), Pasqualini
patent: 5652536 (1997-07-01), Nookala et al.

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