Universal clock generator using delay lock loop

Details Universal clock generator using delay lock loop Universal clock generator using delay lock loop

2003-05-27

2004-09-28

Nguyen, Minh (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Clock or pulse waveform generating

C327S099000, C327S175000, C365S233100

Reexamination Certificate

active

06798266

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to clock generators used in integrated circuits, and more particularly to a universal clock generator using a delay lock loop to generate multiple frequencies of clocks for integrated circuits.
BACKGROUND OF THE INVENTION
Clock generators are widely used in digital integrated circuits to generate clock signals for synchronizing the operation of various components in digital circuits at the frequency of the clock. The components in the digital circuits typically synchronize their operation with one another at the rising edges or falling edges of the clock signals.
Certain components in digital circuits may require operation at frequencies different from those required in other components. In such cases, digital circuits typically include a plurality of clock generators for generating clock signals at different frequencies.
Conventional clock generators use a phase-locked-loop (PLL) scheme and/or a digital divider to generate clock signals. However, conventional clock generators have the disadvantage that it is difficult to control the duty cycles of the clocks generated and that multiple clock generators are sometimes required to generate clock signals with different frequencies.
For example, the duty cycles of the clocks generated by a conventional digital divider are difficult to control, because they are limited to the integer divider numbers of the digital dividers generating the clocks. For instance, a digital divider of 3 (integer) can be designed but a divider of 3.33 (real number) cannot. And, in the case of a digital divider of 3, the duty cycle is limited to 66.6% or 33.3% due to the 2:1 natural integer.
Furthermore, PLLs are not amenable to generating clocks of high frequency since they have to run at an even higher frequency and then their output signals have to be divided down by an integer to the desired clock frequency. In addition, multiple PLLs are required to generate multiple clocks of different frequencies.
Therefore, there is a need for a clock generator that can generate multiple frequencies. There is also a need for a clock generator that can be easily programmed to generate clocks of desired frequencies. There is also a need for a clock generator that can generate clocks of which the duty cycle is easy to control.
SUMMARY OF INVENTION
The present invention provides a universal clock generator that generates a plurality of clocks of different frequencies using a delay lock loop (DLL) and a sequencer. In a first embodiment, the delay lock loop receives an input clock signal having an input clock frequency and generates a plurality of delayed clock signals each having a frequency same as the input clock frequency but having a different phase delay in relation to the input clock signal. The sequencer in the first embodiment receives the delayed clock signals and selects one of the delayed clock signals at any moment according to a predetermined sequence to generate an output clock signal having an output clock frequency corresponding to the predetermined sequence.
The clock generator according to the first embodiment may also comprise a token generator that receives the output clock signal from the sequencer and generates control signals for controlling the sequencer. The control signals generated by the token generator control the sequencer to select only one of the delayed clock signal at each cycle of the output clock signal according to the predetermined sequence. The clock generator may also include a divide-by-2 circuit that receives the output clock signal from the sequencer, reduces the output clock frequency in half, and acdjusts the duty cycle of the output clock signal to fifty percent.
In a second embodiment, the clock generator generates a plurality of clock signals having different frequencies using a delay lock loop, a first sequencer, and a second sequencer. The delay lock loop receives an input clock signal having an input clock frequency and generates a plurality of delayed clock signals each having a frequency that is the same as the input clock frequency but at a different phase delay in relation to the input clock signal. The first sequencer receives the delayed clock signals and selects one of the delayed clock signals at any moment according to a first sequence to generate a first output clock signal having a first output clock frequency corresponding to the first sequence. The second sequencer receives the delayed clock signals and selects one of the delayed clock signals at any moment according to a second sequence to generate a second output clock signal having a second output clock frequency corresponding to the second sequence.
The clock generator of the second embodiment may further comprise a first token generator that receives the first output clock signal from the first sequencer and generates first control signals for controlling the first sequencer, and a second token generator that receives the second output clock signal from the second sequencer and generates second control signals for controlling the second sequencer. The first control signals control the first sequencer to select only one of the delayed clock signals at each cycle of the first output clock signal according to the first sequence, and the second control signals control the second sequencer to select only one of the delayed clock signals at each cycle of the second output clock signal according to the second sequence.
The present invention also provides a method of generating an output clock signal using a delay lock loop and a sequencer. The method receives an input clock signal having an input clock frequency and generates a plurality of delayed clock signals each having a frequency same as the input clock frequency but a different phase delay in relation to the input clock signal. The method selects one of the delayed clock signals at any moment according to a predetermined sequence to generate the output clock signal having an output clock frequency corresponding to the predetermined sequence. The method may also reduce the output clock frequency in half and adjust the duty cycle of the output clock signal to fifty percent.
In another embodiment, the present invention also provides a method of generating a plurality of output clock signals using a DLL and a plurality of sequencers. The method receives an input clock signal having an input clock frequency and generates a plurality of delayed clock signals each having a frequency same as the input clock frequency but a different phase delay in relation to the input clock signal. The method selects one of the delayed clock signals at any moment according to a first sequence to generate a first output clock signal having a first output clock frequency corresponding to the first sequence, and in parallel selects one of the delayed clock signals at any moment according to a second sequence to generate a second output clock signal having a second output clock frequency corresponding to the second sequence. The method may also reduce the first output clock frequency in half and adjust the duty cycle of the first output clock signal to fifty percent, and in parallel reduce the second output clock frequency in half and adjusting the duty cycle of the second output clock signal to fifty percent as well.
The clock generator according to the present invention has the advantage that it is capable of generating very versatile clock signals having different frequencies by use of a plurality of delayed clock signals output from the DLL having different phase delays in a controlled way to select the delayed clock signals according to different sequences. the frequency of the output clock signal is controlled by the sequence in which the clock signals are selected.


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