Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
1999-08-04
2002-06-18
Nguyen, Vinh P. (Department: 2858)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S765010
Reexamination Certificate
active
06407564
ABSTRACT:
FIELD OF THE INVENTION
The present invention generally relates to a ball grid array (BGA) test board for use in failure analysis of IC chips and a method of using the board and more particularly, relates to an universal BGA test board that can be used on both the top and bottom sides of the board for testing for any size IC chips and a method of using such universal BGA test board.
BACKGROUND OF THE INVENTION
In the semiconductor fabrication technology, the capability and effectiveness of performing a failure analysis on a semiconductor chip package are very important. When an integrated circuit (IC) chip fails in service, the nature and the cause for such failure must be determined in order to prevent the reoccurrence of such failure in similar products.
An IC chip is normally built on a silicon base substrate with many layers of insulating materials and metal interconnections. This type of multi-layer structure becomes more important in modem IC devices such as high density memory chips where, in order to save chip real estate, the active device is built upwards in many layers forming transistors, capacitors and other logic components.
When an IC device is found defective during a quality control test, various failure analysis techniques can be used to determine the cause of such failure. Two of the more recently developed techniques for performing failure analysis are the infrared light emission microscopy and the light-induced voltage alteration (LIVA) imaging technique. In the infrared light emission light analysis, an infrared light transmitted through a substrate silicon material is used to observe from the backside of an IC the failure mode of the circuit. For instance, at a magnification ratio of 100×, a failure point in the circuitry can be located. The LIVA imaging technique can be used to locate open-circuited and damaged junctions and to image transistor logic states. The LIVA images are produced by monitoring the voltage fluctuation of a constant current power supply when a laser beam is scanned over an IC. A high selectivity for locating defects is possible with the LIVA technique.
Another method that has become more common in failure analysis of IC chips is the scanning optical microscopy (SOM). The high focusing capability of SOM provides improved image resolution and depth comparable to conventional optical microscopy. It is a useful tool based on the laser beam's interaction with the IC. The SOM technique enables the localization of photocurrents to produce optical beam induced current image that show junction regions and transistor logic states. Several major benefits are made possible by the SOM method when compared to a conventional scanning electron microscopy analysis. For instance, the benefits include the relative ease of making IC electrical connection, the no longer required vacuum system and the absence of ionizing radiation effects.
Even though the above discussed techniques are effective in identifying failure modes in IC circuits, the techniques require elaborate and complicated electronic equipment which are generally costly and not readily available in a semiconductor fabrication facility. It is therefore desirable to have available a method and apparatus that can be easily carried out without expensive laboratory equipment such that the apparatus can be installed in any fabrication facilities. One such apparatus utilizes a liquid crystal coating layer for the identification of failure sites in an IC chip. For instance, in the method wherein a liquid crystal layer is used for the identification of failure sites, a liquid crystal material is frequently coated on top of an IC chip or an IC package. A typical test set up is shown in FIG.
1
.
As shown in
FIG. 1
, a typical liquid crystal detection apparatus
10
is provided. The apparatus
10
generally includes a heater
12
and an optical microscope
14
. On a top surface
16
of the heater
12
, an IC package
20
is positioned under the microscope
14
. The IC package
20
may be a plastic quad flat pack (PQFP) or any other packaged IC device. The IC package
20
, shown in
FIG. 1
, is completed with bonding pads
22
and bonding wires
24
. In the middle portion of the package
20
are IC circuits that contain failure sites need to be identified by a liquid crystal method. In the conventional method, a liquid crystal material is first coated to the top surface
26
of the IC package
20
. The IC package
20
is then positioned on top of the heater
12
which can be heated at a pre-programmed heating rate to a specific temperature. The IC package
20
, together with the coated liquid crystal layer (not shown) is normally heated to a temperature just below the clear/opaque transition temperature of the liquid crystal material. For instance, a suitable temperature would be approximately between about 5° and about 10° below the transition temperature of the liquid crystal. After the IC package
20
is heated to the predetermined temperature, a pre-selected voltage is applied to the IC circuit through bonding wires
24
. The IC circuit, upon receiving such a voltage, heats up at any short or leakage positions. A hot spot is thus generated at each of the locations. The liquid crystal material immediately adjacent, or contacting the hot spots has its temperature raised above its transition temperature and transforms from an opaque state to a clear state. As a result, bright spots in the liquid crystal layer, i.e., on the IC package, show up to indicate the failure sites in the package.
Several drawbacks have been noted in the practice of the liquid crystal detection method. One of the obvious drawbacks is that when testing IC chips of different sizes, a single test board cannot be used for all IC chips. A different test board is required for testing chips of different sizes such that the chip can be mounted on the board for making electrical connections by wire bonding with the conductive leads provided on the test board. Based on the large number of IC chips of different sizes it is a tedious task to supply a large number of test boards that will fit each individual chip. Ideally, a universal test board should be designed such that it will fit different sizes of IC chips for testing.
It is therefore an object of the present invention to provide an universal test board for performing failure analysis on IC chips that does not have the drawbacks or shortcomings of the conventional test boards.
It is another object of the present invention to provide an universal test board for failure analysis that is constructed in a ball grid array configuration such that probe needles can be used to make electrical contact with the ball pads in the ball grid array.
It is a further object of the present invention to provide an universal BGA board for performing failure analysis that fits any size of IC chips.
It is another further object of the present invention to provide an universal BGA test board for performing failure analysis fits IC chips that have a dimension between about 0.1 cm×0.1 cm and about 1.8 cm×1.8 cm.
It is still another object of the present invention to provide an universal BGA test board for performing failure analysis which is equipped with a multiplicity of elongated conductive leads surrounding a rectangular opening in the board such that elongated leads can be severed and shortened by enlarging the rectangular opening to fit a large IC chip.
It is yet another object of the present invention to provide an universal BGA test board for performing failure analysis which has a top side and a bottom side both equipped with a multiplicity of conductive leads, ball pads and conductive traces connecting thereinbetween such that a small chip can be tested on one side and a large chip can be tested on the opposite side of the test board.
It is still another further object of the present invention to provide a method for failure analysis by using an universal BGA test board wherein the test board can be connected electrically to an IC chip on both sides of the board and to fit
Nguyen Vinh P.
Taiwan Semiconductor Manufacturing Co. Ltd.
Tung & Associates
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