Unity gain interpolator for delay locked loops

Details Unity gain interpolator for delay locked loops Unity gain interpolator for delay locked loops

2003-01-08

2004-09-07

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Having specific delay in producing output waveform

C327S561000, C330S130000

Reexamination Certificate

active

06788123

ABSTRACT:

BACKGROUND OF THE INVENTION
As the frequencies of modern computers continue to increase, the need to rapidly transmit data between chip interfaces also increases. To accurately receive data, source synchronous transmission may be used in which a clock signal is transmitted to help recover the data. The clock signal determines when a data signal should be sampled by a receiver's circuits.
The clock signal may transition at the beginning of the time the data signal is valid. The receiver often requires, however, that the clock signal transition during the middle of the time that the data signal is valid. Also, the transmission of the clock signal may degrade as it travels from its transmission source. In both circumstances, a delay locked loop, or DLL, can regenerate a copy of the clock signal at a fixed phase offset from the original clock signal.
FIG. 1
shows a typical source synchronous communication system (
100
). Data signals that are K bits wide are transmitted from circuit A (
12
) to circuit B (
34
) on a data path (
14
). To aid in the recovery of the transmitted data signals, a clock signal is transmitted on a clock path (
16
) at a similar time as the data signal. Although not shown, the communication system (
100
) could also have a path to transmit data signals from circuit B (
34
) to circuit A (
12
) along with an additional clock signal (not shown).
In
FIG. 1
, a DLL (
40
) generates a copy of the clock signal from the clock path (
16
) with a valid state and with a phase offset to be used by other circuits. For example, the DLL (
40
) outputs the copy of the clock signal with a predetermined phase offset to cause a latch device to sample the data signal. A latch device may be, for example, a flip-flop (
38
) as shown in FIG.
1
. When the copy of the clock signal transitions, the flip-flop (
38
) samples the output of an amplifier (
36
) that amplifies the data signal on the data path (
14
). The latched signal from the flip-flop (
38
) is provided to other circuits on circuit B (
34
) as a local data signal (
42
).
The DLL (
40
) is arranged to maintain a constant phase offset between the clock signal input to the DLL (
40
) and the clock signal output from the DLL (
40
). The DLL (
40
) uses a delay stage to delay the clock signal input to the DLL (
40
). The DLL (
40
) may be required to provide relatively fine resolution adjustments to an amount of delay produced.
FIG. 2
shows a typical delay stage (
200
). The delay stage (
200
) may include a delay chain (
250
) and an interpolator (
208
). The delay chain (
250
) may include a plurality of delay elements (
202
,
204
,
206
). Each delay element (
202
,
204
,
206
) delays an input clock signal at an output of the delay element (
202
,
204
,
206
) by an amount of delay. For example, an input clock signal on signal path (
201
) is input to the delay element (
202
). A clock signal from the delay element (
202
) is output on a signal path (
203
). The clock signal on the signal path (
203
) is input to delay element (
204
). A clock signal from the delay element (
204
) is output on a signal path (
205
). Additional delay elements and signal paths, for example delay element (
206
) and signal path (
207
), may be added to the delay chain (
250
). The delay of each delay element (
202
,
204
,
206
) and the number of signal paths (
201
,
203
,
205
,
207
) may determine the amount of delay of the delay chain (
250
).
In
FIG. 2
, the delay chain (
250
) can produce several amounts of delay. By designing a chain of delay elements (
202
,
204
,
206
), delays can be produced with different delay amounts on signal paths (
201
,
203
,
205
,
207
) connected between the delay elements (
202
,
204
,
206
). For example, the delay amount on the signal path (
205
) is the result of a delay amount of delay element (
204
) in addition to the amount of delay on signal path (
203
).
In
FIG. 2
, a clock interpolator (
208
) receives the clock signals on the signal paths (
201
,
203
,
205
,
207
). The clock interpolator (
208
) is used to improve the granularity of the delay amounts. The clock interpolator (
208
) may select two successive clock signals on the signal paths (
201
,
203
,
205
,
207
) and produce a clock signal output (
209
) with a temporal delay in between the two successive clock signals from the signal paths (
201
,
203
,
205
,
207
). The output clock signal on output clock path (
209
) may be used by other circuits, for example, a latch device.
The clock interpolator (
208
) receives control signals on control signal paths (
211
) that are M bits wide. The control signals may carry digital and/or analog signals. The control signals indicate the desired amount of delay between the input clock signal and output clock signal. Depending on the desired delay, the interpolator (
208
) may output on output clock path (
209
) one of the clock signals from the signal paths (
201
,
203
,
205
,
207
) or an interpolated signal having a temporal delay in between two of the clock signals from the signal paths (
201
,
203
,
205
,
207
).
FIG. 3
shows a schematic diagram of a typical interpolator (
300
). The interpolator (
300
) uses a pair of differential amplifiers (
350
,
360
) to generate complementary output clock signals &phgr;
3
(
311
) and &phgr;
3
—
(
313
) with a temporal delay in between two input clock signals. Complementary input clock signals &phgr;
1
(
303
) and &phgr;
1
—
(
305
) are input to the first differential amplifier (
350
). Clock signal &phgr;
1
(
303
) connects to an n-channel transistor (
306
) and clock signal &phgr;
1
—
(
305
) connects to an n-channel transistor (
308
). Complementary input clock signals &phgr;
2
(
307
) and &phgr;
2
—
(
309
) are input to the second differential amplifier (
360
). Clock signal &phgr;
2
(
307
) connects to an n-channel transistor (
310
) and clock signal &phgr;
2
—
(
309
) connects to an n-channel transistor (
312
).
In
FIG. 3
, during a clock signal transition of complementary input clock signals &phgr;
1
(
303
) and &phgr;
1
—
(
305
), one of the n-channel transistors (
306
,
308
) will conduct more current than the other. The one of the n-channel transistors (
306
,
308
) that conducts more current will pull its respective complementary output clock signals &phgr;
3
—
(
313
) and &phgr;
3
(
311
) toward ground. The other one of the complementary output clock signals &phgr;
3
—
(
313
) and &phgr;
3
(
311
) will tend toward V
DD
. The amount of current conducted through one of the n-channel transistors (
306
,
308
) is determined by fixed value resistors (
302
,
304
) and a value of a current source (
314
). The current source (
314
) is controlled by a control voltage potential V
CNTL
(
315
).
During a clock signal transition of complementary input clock signals &phgr;
2
(
307
) and &phgr;
2
—
(
312
), one of the n-channel transistors (
310
,
312
) will conduct more current than the other. The transition of complementary input clock signals &phgr;
2
(
307
) and &phgr;
2
—
(
312
) are temporally delayed after the transition of complementary input clock signals &phgr;
1
(
303
) and &phgr;
1
—
(
305
). The one of the n-channel transistors (
310
,
312
) that conducts more current will pull its respective complementary output clock signals &phgr;
3
—
(
313
) and &phgr;
3
(
311
) toward ground. The other one of the complementary output clock signals &phgr;
3
—
(
313
) and &phgr;
3
(
311
) will tend toward V
DD
. The amount of current conducted through one of the n-channel transistors (
310
,
312
) is determined by the fixed value resistors (
302
,
304
) and a value of a current source (
316
). The current source (
316
) is controlled by the control voltage potential V
CNTL
(
315
).
By controlling the control voltage potential V
CNTL
(
315
), the mixing weight between the complementary input clock signals &phgr;
1
(
303
) and &phgr;
1
—
(
305
) and complementary input clock signals &phgr;
2
(
307
) and &phgr;
2
—
(
312
) may be adjusted. The slew rate of the complementary output cl

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