Unity-gain CMOS/SOS zero-offset buffer

Details Unity-gain CMOS/SOS zero-offset buffer Unity-gain CMOS/SOS zero-offset buffer

1989-05-24

1990-12-18

Mottola, Steven

Amplifiers

With semiconductor amplifying device

Including field effect transistor

330 85, H03F 316

Patent

active

049789252

ABSTRACT:
A near unity gain, essentially zero-offset, high input impedance, relatively low output impedance, fast responding buffer circuit uses first and second essentially identical n-channel depletion mode MOS transistors with the drain-source circuitries serially connected together and with the gate and source of the second transistor connected together. A first feedback circuit, which uses a first n-channel enhancement mode MOS transistor as a voltage level shifter and a third n-channel depletion mode MOS transistor as a source follower, is connected between the source and drain of the first transistor. A second feedback circuit, which uses a second n-channel enhancement mode MOS transistor as a voltage level shifter and a fourth n-channel depletion mode MOS transistor as a source follower, is connected between the source and drain of the second transistor. The gate and source of the first transistor serve as the buffer input and output terminals, respectively.

REFERENCES:
patent: 4612514 (1986-09-01), Shigaki et al.
patent: 4714845 (1987-12-01), Devecchi et al.

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