Unitary-gain final stage particularly for monolithically integra

Amplifiers – With semiconductor amplifying device – Including differential amplifier

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330260, H03F 345

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active

052163814

ABSTRACT:
Unitary-gain final stage particularly for monolithically integratable power amplifiers, which comprises a pair of final N-channel MOS power transistors. The first transistor has its drain terminal connected to a supply voltage and its source terminal connected to the drain terminal of the second transistor. The source terminal of the second transistor is connected to the ground. The output terminal of the power amplifier is connected between the source terminal of the first transistor and the drain terminal of the second transistor. The final stage furthermore comprises a high-gain feedback differential amplifier which has its non-inverting input terminal connected to the input of the power amplifier, its inverting input terminal connected to the output terminal of the differential amplifier and its output terminal connected to the gate terminal of the second transistor. A leveling circuit is furthermore connected to the gate terminal of the second transistor. A third MOS transistor has its source terminal connected to the input of the amplifier, and its gate terminal and drain terminal are connected to the gate terminal of the first transistor and to a first driven current source.

REFERENCES:
patent: 3987369 (1976-10-01), Yokoyama
patent: 4241313 (1980-12-01), Takehara
patent: 4370623 (1983-01-01), Nagasawa
Calzolari et al, "Integrated NMOS Output State With Low Output Impedance," Electronics Letters, vol. 17, No. 6, Mar. 19, 1981, pp. 218 -220.
Patent Abstracts of Japan vol. 6, No. 42 Mar. 16, 1982.
Electronics World and Wireless World (GB) vol. 96, No. 1655 Sep. 1990 pp. 760-764.
IEEE Transact. On Consumer Electronics vol. CE-28, No. 4, Nov. 1982 pp. 546-552.

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