Unit for switching data transmitted by asynchronous time-divisio

Details Unit for switching data transmitted by asynchronous time-divisio Unit for switching data transmitted by asynchronous time-divisio

1988-11-28

1990-07-03

Olms, Douglas W.

Multiplex communications

Wide area network

Packet switching

H04Q 1104

Patent

active

049397206

ABSTRACT:
The invention concerns a unit for switching data transmitted by asynchronous time-division multiplexing comprising receive circuits (CRl/i) supplying cells received via input links, transmit circuits (CTl/j) transmitting retransmitted cells on output links, a buffer memory (MT) storing the received cells and delivering the cells to be retransmitted and a buffer memory addressing device (SMT) including a write address source (SAE) and a read address source (fsl/j).
The switching unit further comprises a write disabling circuit (pi) conditioned by a signal (adl) derived from the content of at least one received cell or a signal (tle) derived from the absence of any received cell and supplying a disabling signal (spi) and the address source includes a disabling device (pac, pal) influenced by the disabling signal (spi) so that no memory location is then occupied in the buffer memory (MT).

REFERENCES:
patent: 3979733 (1976-09-01), Fraser
patent: 4312063 (1982-01-01), Warner
patent: 4491945 (1986-01-01), Turner
patent: 4520479 (1985-05-01), Grima et al.
patent: 4566095 (1986-01-01), Devault et al.
patent: 4603416 (1986-07-01), Servel et al.
patent: 4703477 (1987-10-01), Adelmann et al.
patent: 4759012 (1988-07-01), Suzuki
patent: 4788679 (1988-11-01), Kataoka et al.
Proceedings Computer Networking Symposium, S. Nojima et al., "High Speed Packet Switching Network for Multi-Media Information", pp. 141-150, IEEE, Washington, D.C. Nov. 17-18, 1986.
English Language Equivalent of EP 0 300 876 as filed in Australia (AU 1979388).

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