Active solid-state devices (e.g. – transistors – solid-state diode – Physical configuration of semiconductor – With peripheral feature due to separation of smaller...
Reexamination Certificate
2002-03-16
2004-09-14
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Physical configuration of semiconductor
With peripheral feature due to separation of smaller...
C257S680000, C257S729000, C257S730000, C257S678000, C257S909000, C359S626000, C372S092000, C372S097000, C372S098000, C310S309000, C385S016000, C385S008000, C385S033000
Reexamination Certificate
active
06791162
ABSTRACT:
FIELD OF THE INVENTION
The present invention generally relates to the field of microelectromechanical systems and, more particularly, to a unit cell that facilitates the layout of at least a portion of such a system.
BACKGROUND OF THE INVENTION
There are a number of microfabrication technologies that have been utilized for making microstructures (e.g., micromechanical devices, microelectromechanical devices) by what may be characterized as micromachining, including LIGA (Lithography, Galvonoforming, Abforming), SLIGA (sacrificial LIGA), bulk micromachining, surface micromachining, micro electrodischarge machining (EDM), laser micromachining, 3-D stereolithography, and other techniques. Bulk micromachining has been utilized for making relatively simple micromechanical structures. Bulk micromachining generally entails cutting or machining a bulk substrate using an appropriate etchant (e.g., using liquid crystal-plane selective etchants; using deep reactive ion etching techniques). Another micromachining technique that allows for the formation of significantly more complex microstructures is surface micromachining. Surface micromachining generally entails depositing alternate layers of structural material and sacrificial material using an appropriate substrate (e.g., a silicon wafer) which functions as the foundation for the resulting microstructure. Various patterning operations (collectively including masking, etching, and mask removal operations) may be executed on one or more of these layers before the next layer is deposited so as to define the desired microstructure. After the microstructure has been defined in this general manner, the various sacrificial layers are removed by exposing the microstructure and the various sacrificial layers to one or more etchants. This is commonly called “releasing” the microstructure from the substrate, typically to allow at least some degree of relative movement between the microstructure and the substrate.
It has been proposed to fabricate various types of optical switch configurations using various micromachining fabrication techniques. One of the issues regarding these types of optical switches is the number of mirrors that may be placed on a die. A die is commonly referred to as that area defined by one field of a stepper that is utilized to lay out the die. Reducing the size of the mirrors in order to realize the desired number of mirrors on a die may present various types of issues. For instance, there are of course practical limits as to how small the mirrors can be fabricated, which thereby limits the number of ports for the optical switch. Also, the optical requirements of the system using the mirrors may require mirrors larger than some minimum size. Therefore, it may not be possible to fabricate the optical switch with a certain number of ports using a single die. This presents a challenge regarding how to route electrical signals.
BRIEF SUMMARY OF THE INVENTION
The present invention generally relates to a unit cell. This unit cell may be used to create a layout for at least part of a microelectromechanical system. Although this unit cell will contain at least a plurality of electrical lines, conductors, traces, or the like (hereafter “traces”), various microstructure assemblies (e.g., one or more electrical load-based microstructures) may be included as part of the unit cell as well. Generally, the unit cell meets a number of predetermined boundary conditions such that once this unit cell is drawn or otherwise created, it may be simply copied, translated, and pasted an appropriate number of times to define at least part of a microelectromechanical system. This process may be collectively characterized as tiling the unit cell. In any case, a plurality of structurally identical unit cells will be placed in end-to-end relation in one or more rows as desired/required. Adjacent unit cells in each row will be electrically interconnected based upon the unit cell satisfying the predetermined boundary conditions.
A first aspect of the present invention is embodied by a chip that is formed using a plurality of unit cells. Each unit cell is structurally identical, and therefore only one unit cell need be described. The unit cell includes first and second sides. A plurality of these unit cells may be disposed in end-to-end relation to define a row that at least generally extends in a first direction. More specifically, the first side and second side of each adjacent pair of unit cells in a given row will be disposed up against each other such that the first and second sides of the unit cell will be spaced from each other in the first direction. In the event that a row of unit cells is characterized as being laterally extending (e.g., extending along/defining a width dimension for the chip), the first and second sides of the unit cell could then be characterized as being laterally spaced. The unit cell includes a plurality of first electrical traces that extend between its first and second sides. The unit cell also includes a plurality of second electrical traces. These second electrical traces extend from any of the first and second sides and terminate within the unit cell (i.e., at an interior location). Therefore, both ends of each first electrical trace are disposed on a perimeter of the unit cell. However, only one end of each second electrical trace is disposed on a perimeter of the unit cell.
There are a number of boundary conditions associated with the unit cell of the first aspect. For ease of description of these boundary conditions, a row of unit cells on the chip will be characterized as at least generally extending in a first dimension (e.g., a width dimension for the chip). A second dimension is perpendicular to this first dimension (e.g., a height dimension for the chip). The first and second dimensions may be such that they collectively define a plan view of the chip formed from the unit cells. The required boundary conditions for the unit cell are as follows: 1) each first electrical trace at the first side of the unit cell, and either a different first electrical trace at the second side of the unit cell or a second electrical trace at the second side of the unit cell, are disposed along a common reference line that is parallel with the first dimension; 2) each first electrical trace at the second side of the unit cell, and either a different first electrical trace at the first side of the unit cell or a second electrical trace at the first side of the unit cell, are disposed along a common reference line that is parallel with the first dimension; 3) each second electrical trace that is disposed on the first side of the unit cell and one first electrical trace on the second side of the unit cell are disposed along a common reference line that is parallel with the first dimension; and 4) each second electrical trace that is disposed on the second side of the unit cell and one first electrical trace on the first side of the unit cell are disposed along a common reference line is parallel with the first dimension.
Various refinements exist of the features noted in relation to the first aspect of the present invention. Further features may also be incorporated in the present invention as well. These refinements and additional features may exist individually or in any combination. The noted boundary conditions facilitate the electrical interconnection of adjacent unit cells in a row from which a chip may be formed. Any number of first and/or second electrical traces may exist within the unit cell and still satisfy the noted boundary conditions. However, in one embodiment, there is an even number of first electrical traces, an even number of second electrical traces, or both. One or more second electrical traces may extend from the first side of the unit cell, one or more second electrical traces may extend from the second side of the unit cell, or both and still satisfy the above-noted boundary conditions as well. In one embodiment, none of the traces in the unit cell cross over each other.
Additional boundary conditions may e
Erdem Fazli
Flynn Nathan J.
Marsh & Fischmann & Breyfogle LLP
MEMX, Inc.
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