Uniformity improvement of high aspect ratio contact by stop...

Details Uniformity improvement of high aspect ratio contact by stop... Uniformity improvement of high aspect ratio contact by stop...

1998-12-07

2001-05-08

Mills, Gregory (Department: 1763)

Cleaning and liquid contact with solids

Processes

Including application of electrical radiant or wave energy...

C134S001200, C438S695000, C438S696000, C438S723000, C438S724000, C438S734000, C438S744000, C438S743000

Reexamination Certificate

active

06227211

ABSTRACT:

FIELD OF THE INVENTION
The invention relates to the plasma etching of a silicon wafer in the manufacture of integrated circuits.
DESCRIPTION OF THE PRIOR ART
As the density of circuit components contained within a semiconductor die has increased and the circuit components have decreased in size and are spaced closer together, it has become increasingly difficult to access selectively a particular region of the silicon wafer through the various layers that are typically superimposed on the surface of the silicon wafer without undesired interference with other active regions.
It is especially important to have a technology that can etch openings that have essentially vertical walls, most notably when the openings are to extend deeply into the surface layers. Special care must also be taken to insure that the profile of the lower section or bottom of the opening resembles a straight line in order to reduce thickness difference in the underlying layers. To this end, it is critically important to select a stop layer (that has a restraining influence on the etching process) within the semiconductor structure that enhances the linearity or straight-line profile of the bottom of the etched hole.
Additionally, to tolerate some misalignment in the masks used to define such openings, it is advantageous to provide protection to regions that need isolation but that inadvertently lie partially in the path of the projected opening. To this end it is sometimes the practice to surround such regions with a layer of material that resists etching by the process being used to form the openings. Accordingly, a technology that provides the desired results will need an appropriate choice both in the materials used in the layers and the particular etching process used with the materials chosen.
Dry etching, such as plasma etching and reactive ion etching, has become the technology of choice in patterning various layers that are formed over a silicon wafer as it is processed to form therein high density integrated circuit devices. This is because it is a process that not only can be highly selective in the materials it etches, but also highly anisotropic. This makes possible etching with nearly vertical sidewalls.
Basically, in plasma etching as used in the manufacturing of silicon integrated devices, a silicon wafer on whose surface various layers have been deposited is positioned on a first electrode in a chamber that also includes a second electrode spaced opposite the first. As a gaseous medium that consists of one or more gasses is flowed through the chamber, an r-f voltage, which may include components at different frequencies, is applied between the two electrodes to create a discharge that ionizes the gaseous medium and that forms a plasma that etches the wafer. By appropriate choice of the gasses of the gaseous medium and the parameters of the discharge, selective and anisotropic etching is achieved.
While elaborate theories have been developed to explain the plasma process, in practice most of such processes have been developed largely by experimentation involving trial and error of the otherwise relatively poor predictability of results.
Moreover, because of the number of variables involved and because most etching processes depend critically nor only on the particular materials to be etched bur also on the desired selectivity and anisotropy, such experimentation can be time consuming while success often depends on chance.
U.S. Pat. No. 5,783,496 (Flanner et al.) shows an etch process of a contact that stops on a Si
3
N
4
layer on gates. Flanner details a special C
x
HyF
z
containing gas
2
step process.
U.S. Pat. No. 5,286,344 (Bialock et al.) shows a process for a contact by etching SiO
2
and stopping on Si
3
N
4
.
U.S. Pat. No. 5,691,246 (Becker et al.) discloses an in-situ etch process of a contact through SiO
2
and Si
3
N
4
.
U.S. Pat. No. 5,366,590 (Kadomura) shows a SiO
2
and Si
3
N
4
contact etch process.
SUMMARY OF THE INVENTION
It is the primary objective of the present invention to improve uniformity of the thickness of the stop layer at the bottom of etched holes after contact hole processing has been completed.
It is another objective of the present invention to considerably reduce presently required over-etch time when etching contact holes.
It is another objective of the present invention to reduce the integrated circuit Resistive Capacitive time constant.
It is another objective of the present invention to reduce integrated circuit junction leakage current.
It is another objective of the present invention to improve integrated circuit electrical performance.
It is another objective of the present invention to improve integrated circuit reliability.
FIG. 1
shows a cross section of Prior Art etched contact holes
20
. These contact holes are created in a semiconductor-layered construction where the presently used Plasma Enhanced Tetra-Ethyl-Ortho-Silicate (PETEOS) is used as a stop layer. The stop layer serves the purpose of controlling or “slowing down” the etching of the contact hole and forms one of the layers within the semiconductor layered construction. As such the stop layer is deposited close to where the bottom
30
of the contact hole is designed to be without however being the last layer or bottom of the hole. The present profile of the contact openings has been obtained using the conventional etching sequence for 0.025 embedded DRAM circuits. Six gases are used for this etching sequence which resulted in poor underlayer selectivity. Special attention must also be paid to the contact opening profile. A poor contact opening profile results in poor contact barrier uniformity of the sidewalls
10
of the holes.
FIG. 1
clearly shows the over-etching
30
that occurred in the underlying, typically TiSix, substrate.
FIG. 2
shows an enlargement of the lower section of a Prior Art contact hole. It is clear that section
40
of the bottom of the contact hole shows considerable bowing or hollowing out. In other words, the etching of the contact hole has not created a flat profile which means that the contact hole cuts into underlying layers. This is, from an electrical design point of view, a very undesirable profile. The bottom profile of the contact hole ideally is square and must not protrude into lower lying layers.
FIG. 3
shows Prior Art application of a layer
50
of PETEOS within a semiconductor structure.
FIG. 3
demonstrates that the stop layer
50
of present design can be located close to the bottom of the etched contact hole without however forming the bottom of this hole, see holes
32
and
34
. For holes
36
and
38
the stop layer
50
does not form part of the process of etching these holes.
FIG. 3
is a cross section of a DRAM structure wherein
1
is a storage electrode of a memory cell,
2
forms a trench capacitor,
3
can be a bit line,
4
can be a word line,
5
can be a trench cell,
6
can be a trench plug and
7
can be a capacitor contact plate.
The poor uniformity of Interlevel Dielectric Deposition (ILD) thickness for High Aspect Ratio (HAR) contact after Chemical Mechanical Planarization (CMP) will cause serious underlayer loss due to the longer over-etching time that is required to compensate for thickness differences within the wafer. Prior Art uses 1.5K Plasma Enhanced Tetra-Ethyl-Ortho-Silicate (PETEOS) to serve as a stop layer and thus reduce underlayer loss. The present invention teaches using a non-silicon oxide containing Si
3
N
4
/SiON as a stop layer since non-silicon oxide assures uniformity of the thickness of the bottom layer of the contact hole after the contact hole has been etched into the semiconductor construct. This is due to the high selectivity of non-silicon oxide during contact hole processing. That is the Oxide, which is used during the contact hole etching process to form the contact hole, does not cause a depletion of the stop layer if non-silicon oxide is used as stop layer. The Prior Art use of 1.5K PETEOS for stop layer shows a considerable variation in the inter-level layer thickness after completion

Affiliated with

Also associated with

Rating

Uniformity improvement of high aspect ratio contact by stop... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Uniformity improvement of high aspect ratio contact by stop..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Uniformity improvement of high aspect ratio contact by stop... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2509072