Electricity: electrical systems and devices – Safety and protection of systems and devices – Load shunting by fault responsive means
Reexamination Certificate
2007-01-30
2007-01-30
Jackson, Stephen W. (Department: 2836)
Electricity: electrical systems and devices
Safety and protection of systems and devices
Load shunting by fault responsive means
C361S111000
Reexamination Certificate
active
10345325
ABSTRACT:
An electrostatic discharge protection circuit. The electrostatic discharge (ESD) circuit utilizes inductors and resistors added to sources of multiple fingers of the NMOS transistor, which is triggered by some feedback circuit uniformly. When under an ESD zapping, a finger MOS transistor is trigger initially to snapback region owing to its layout or other causes, a voltage drop across the inductor or the resistor connected to the source of the finger MOS transistor is occurred and presented to gates of the other finger MOS transistors by the feedback circuit. Thus, the other finger MOS transistors are turned on.
REFERENCES:
patent: 5134321 (1992-07-01), Mehta
patent: 5670803 (1997-09-01), Beilstein et al.
patent: 5959488 (1999-09-01), Lin et al.
patent: 6445068 (2002-09-01), Sofue et al.
patent: 6462601 (2002-10-01), Chang et al.
patent: 6583972 (2003-06-01), Verhaege et al.
Chuang Che-Hao
Ker Ming-Dou
Lo Wen-Yu
Birch & Stewart Kolasch & Birch, LLP
Jackson Stephen W.
Nguyen Danny
Silicon Integrated Systems Corp.
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