Semiconductor device manufacturing: process – Forming schottky junction
Patent
1998-11-05
2000-08-01
Niebling, John F.
Semiconductor device manufacturing: process
Forming schottky junction
438580, 438758, 438760, H01L 2128
Patent
active
060966297
ABSTRACT:
A method for forming a Schottky diode. There is first provided a silicon layer. There is then formed upon the silicon layer an anisotropically patterned first dielectric layer which defines a Schottky diode contact region of the silicon layer. There is then formed and aligned upon the anisotropically patterned first dielectric layer a patterned second dielectric layer which is formed of a thermally reflowable material. There is then reflowed thermally the patterned second dielectric layer to form a thermally reflowed patterned second dielectric layer having a uniform sidewall profile with respect to the anisotropically patterned first dielectric layer while simultaneously forming a thermal silicon oxide layer upon the Schottky diode contact region of the silicon layer. There is then etched while employing a first etch method the thermal silicon oxide layer from the Schottky diode contact region of the silicon layer while preserving the uniform sidewall profile of the thermally reflowed patterned second dielectric layer with respect to the anisotropically patterned first dielectric layer. There is then formed and thermally annealed upon the thermally reflowed patterned second dielectric layer and the Schottky diode contact region of the silicon layer a metal silicide forming metal layer to form in a self aligned fashion a metal silicide layer upon the Schottky diode contact region of the silicon layer, a protective oxide surface layer upon the metal silicide layer and a metal silicide forming metal layer residue upon the thermally reflowed patterned second dielectric layer. There is then stripped from the thermally reflowed patterned second dielectric layer the metal silicide forming metal layer residue. Finally, there is then etched while employing a second etch method the protective oxide surface layer from the metal silicide layer, where the second etch method also preserves the uniform sidewall profile of the thermally reflowed patterned second dielectric layer with respect to the anisotropically patterned first dielectric layer.
REFERENCES:
patent: 4233337 (1980-11-01), Friedman et al.
patent: 4397079 (1983-08-01), Nagarajan et al.
patent: 4619887 (1986-10-01), Hooper et al.
patent: 5021840 (1991-06-01), Morris
patent: 5117276 (1992-05-01), Thomas et al.
patent: 5268316 (1993-12-01), Robinson et al.
patent: 5296406 (1994-03-01), Readdie et al.
patent: 5619064 (1997-04-01), Cho
patent: 5940726 (1999-08-01), Yu
patent: 5960312 (1999-09-01), Morikawa
Ho Yen-Shih
Tsai Jun-Lin
Ackerman Stephen B.
Lattin Christopher
Niebling John F.
Saile George O.
Szecsy Alek P.
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