Uniform clock timing circuit

Details Uniform clock timing circuit Uniform clock timing circuit

2000-02-16

2001-07-03

Cunningham, Terry D. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Clock or pulse waveform generating

C327S293000, C327S415000

Reexamination Certificate

active

06255884

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to precision clock generation circuits and more particularly to high-speed clock generation in monolithic integrated circuits where close timing between a number of different clock loads is required.
2. Description of the Related Art
There is an ever-growing need to increase the speed at which analog signals can be converted into digital form. One common way to meet the requirement for high speed in analog-to-digital converters (ADC's) has been to use multiple comparators in an arrangement known as a basic flash converter. When implemented using Complementary Metal Oxide Semiconductor (CMOS) technology, such flash ADC's can be operated in the conversion frequency range well above 100 MHz. Several factors have, however, limited the resolution of such converters to below seven bits. These limiting factors include high-speed comparator input offsets and charge from the clock timing circuits feeding back or “blowing back” to the input.
Another important limiting factor in these prior art ADC designs are the non-uniform delays in the wiring associated with the clock inputs. Non-uniform delays in the clock generation circuitry occur whenever the delay from the primary clock generation circuit to the clock input of each comparator is not equal, with the result that irregularities arise in the conversion of rapidly varying analog input signals to digital form.
The errors which result from unequal clock delays are known in the art of flash ADC's as “differential phase errors.” For example, for a
100
MHz flash converter digitizing a 50 MHz sine wave, the time rate of change of a 1 volt peak input signal is equal to 2*pi*50E6, or 315 Megavolts per second. If the converter is to have 8-bit accuracy, the voltage error must be less than ½ bit as a result of differential timing error. Because ½ bit of a 2 volt peak to peak signal digitized to 8-bit accuracy corresponds to a voltage error of 4 millivolts, the differential timing error requirement is 6 picoseconds. It is quite difficult to apply the clock timing signal simultaneously to a 8-bit string of comparators with a timing uniformity of 12 picoseconds.
Accordingly, considerable research effort has been devoted to the task of improving the speed performance of high speed ADC's. Because the basic flash converter suffers from several problems, including the differential phase problem described above, algorithmic or pipelined flash converters have been used in 100 MHz applications. In these converters, clock generation problems are overcome by using only a few comparators, perhaps 16 or 32, in the initial conversion, and then passing the input signal remainders from the first conversion error output to a second and usually a third successive flash stage.
One drawback of such architectures—commonly known as pipelined architectures—is that they require sample-and-hold circuits at each stage. Moreover, although pipelined architectures have high throughput rates, they result in each output being available only after several clock cycles. This output delay prevents the converter from being useful in applications where the full digital output must be delivered in a few nanoseconds.
Another problem associated with existing devices based on multiple comparators is excessive load, which causes difficulties with wire matching. Of course, one way to reduce this problem is simply to reduce the number of comparators, in order to make it easier to match the routing, but one is still faced with the problem of non-uniformities in the devices themselves.
The problems discussed are particularly acute in the design of ADC's, since all circuits must operate at high speeds and with precise synchronization. They also arise, however, in other circuitry where components must operate at high speeds, driven synchronously by a common clock.
What is needed is thus a solution to the problems discussed above, in particularly, of timing skew in high-speed clock generation circuits, and particularly in the clock generation circuits required in high-speed basic flash converters.
SUMMARY OF THE INVENTION
The invention provides a clock timing circuit that has a power supply, a clock generator, a plurality of clocked logical devices, and at least one intermediate driving stage that includes a plurality of intermediate driving devices. The clock generator, the logical devices, and the intermediate driving devices are all powered by the power supply. The clock generator has an output clock signal, each of the clocked logical devices has a clock input, and each intermediate driving device in each intermediate driving stage has an input and an output. The output clock signal is connected to the inputs of the intermediate driving devices in a first stage and the outputs of the intermediate driving devices in a final stage are connected to the clock inputs of the logic devices. A non-branched, electrically conductive trace connects the outputs of the intermediate driving devices in at least one of the intermediate driving stages. In the preferred embodiment of the invention, each non-branched, electrically conductive trace is linear, and is formed of an electrically conductive material such as deposited aluminum or copper.
The preferred application of the invention is in an analog-to-digital converter (ADC), in which the logical devices are comparators. In the most common implementation of the ADC, each intermediate device is then an inverter.


REFERENCES:
patent: 3761826 (1973-09-01), Lowe
patent: 6081148 (2000-06-01), Song

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