Uniform bitline strapping of a non-volatile memory cell

Details Uniform bitline strapping of a non-volatile memory cell Uniform bitline strapping of a non-volatile memory cell

2000-11-22

2001-08-14

Le, Vu A. (Department: 2824)

Static information storage and retrieval

Floating gate

Particular connection

C365S063000

Reexamination Certificate

active

06275414

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of non-volatile memory devices. More particularly, the invention relates to a multi-bit flash electrically erasable programmable read only memory (EEPROM) cell with a bitline.
2. Discussion of Related Art
Memory devices for non-volatile storage of information are currently in widespread use today, being used in a myriad of applications. A few examples of non-volatile semiconductor memory include read only memory (ROM), programmable read only memory (PROM), erasable programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM) and flash EEPROM.
Semiconductor EEPROM devices involve more complex processing and testing procedures than ROM, but have the advantage of electrical programming and erasing. Using EEPROM devices in circuitry permits in-circuit erasing and reprogramming of the device, a feat not possible with conventional EPROM memory. Flash EEPROMs are similar to EEPROMs in that memory cells can be programmed (i.e., written) and erased electrically but with the additional ability of erasing all memory cells at once, hence the term flash EEPROM.
An example of a single transistor Oxide-Nitrogen-Oxide (ONO) EEPROM device is disclosed in the technical article entitled “A True Single-Transistor Oxide-Nitride-Oxide EEPROM Device,” T. Y. Chan, K. K. Young and Chenming Hu, IEEE Electron Device Letters, March 1987. The memory cell is programmed by hot electron injection and the injected charges are stored in the oxide-nitride-oxide (ONO) layer of the device. Other examples of ONO EEPROM devices are disclosed in U.S. Pat. Nos. 5,635,415; 5,768,192 and PCT patent application publication WO 99/07000, the contents of each reference are hereby incorporated herein by reference.
In the case of known NROM devices, such as schematically shown in
FIG. 1
, an NROM cell
100
included a grid of polygates or word lines
102
and buried bitlines
104
. The bitlines
104
were formed in the N+ region of the substrate so that a higher density of bitlines can be formed that region versus when the bitlines were formed in a metal layer. Select transistors
106
were required to be placed every N or N/2 polygates
102
, where N is the number of polygates between contacts
108
. This in the past has required a select transistor
106
being required every 16 or 32 cells in order to reduce the bitline to cell resistance. The bitline resistance in the N+ region limits the number of cells between select transistors.
In the case of flash memory cells with a stacked gate, contacts associated with the cell must be spaced from the polysilicon of the gate. As feature sizes are reduced according to integrated circuit processes, smaller dimensions are required to achieve higher packing densities. Generally, contacts must be spaced apart from the stacked gate so alignment errors do not result in a shorting of the stacked gate with the source contact or the drain contact. The spacing between the contact and gate contributes to the overall size of the flash memory cell.
SUMMARY OF THE INVENTION
One aspect of the invention regards an array of memory cells that includes a plurality of memory cells interconnected via a grid of M wordlines and M bitlines, wherein M=2, 3, 4, 5, . . . and each of the M bitlines is buried. The array further includes a plurality of contacts, wherein each of the plurality of contacts is formed every N wordlines, N =1, 2, 3, . . ., wherein each of the plurality of contacts overlies a gate of a different one of the plurality of memory cells. A strap connects one of the buried bitlines to a gate that underlies one of the plurality of contacts and a select transistor is formed every P wordlines, wherein P is greater than N.
The above aspect of the present invention provides the advantage of decreasing the total cell resistance and increasing the number of cells between select transistors.
The above aspect of the present invention provides the advantage of reducing the total size of an array.
The present invention, together with attendant objects and advantages, will be best understood with reference to the detailed description below in connection with the attached drawings.


REFERENCES:
patent: 4698900 (1987-10-01), Esquivel
patent: 6044015 (2000-03-01), Van Houdt et al.

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