Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system – Timing
Reexamination Certificate
1999-11-18
2004-03-09
Jones, Hugh (Department: 2123)
Data processing: structural design, modeling, simulation, and em
Simulating electronic device or electrical system
Timing
C716S030000, C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06704697
ABSTRACT:
TECHNICAL FIELD
The present invention relates to the field of electronic design automation and circuit timing analysis models. In particular, the present invention pertains to the application of layout parasitic data in a hierarchical timing analysis.
BACKGROUND ART
Integrated circuits can be represented as netlists within electronic design automation systems. A circuit timing analyzer takes a netlist of a circuit and the associated timing information for a circuit, and abstracts them to get a timing representation (“model”) of the circuit. The timing model is then used by a circuit analyzer to estimate the overall performance of the circuit, identify critical paths in the circuit, and find timing violations. Prior art circuit analyzers are described by U.S. Pat. No. 5,740,347, entitled “Circuit Analyzer of Black, Gray and Transparent Elements,” by Jacob Avidan, issued Apr. 14, 1998, and by U.S. Pat. No. 5,790,830, entitled “Extracting Accurate and Efficient Timing Models of Latch-Based Designs,” by Russell B. Segal, issued Aug. 4, 1998, herein incorporated by reference in their entirety.
For analysis purposes, a circuit can be considered as a collection of interconnected functional blocks. A functional block includes the collection of hardware components that make up the circuit as well as the software structures used to represent the circuit, such as nodes (a node being a point of connectivity, including an input or output of the circuit). The circuit can be specified hierarchically, with higher level functional blocks encompassing one or more lower level blocks. A higher level functional block may be a subcircuit composed of other lower level functional blocks that may also be subcircuits. The more the circuit is abstracted, the lower the accuracy of the models becomes.
To facilitate the design and analysis of a complex circuit, a hierarchical timing analysis is typically performed. At the highest level of the hierarchy, the overall circuit is analyzed using a multiplicity of integrated timing models that each represent a functional block at the next lower level. Each of these functional blocks is in turn composed of a multiplicity of timing models that each represent a functional block at the next lower level, and so on.
In practice, the timing modelsare typically created starting at the lowest level of the circuit, from there proceeding level-by-level to the highest level. Each lowest level functional block is designed and analyzed. A timing model is created for each lowest level functional block and these timing models are fed to the next higher level, where the models are integrated and an analysis is performed of an integrated mid-level functional block. Other mid-level functional blocks are similarly formed and analyzed. Each of the mid-level blocks is then represented by a timing model which is fed to the next higher analysis level, and so on until at the highest level the overall circuit can be assembled and analyzed using a multiplicity of integrated timing models each representing relatively large functional blocks.
Prior Art
FIG. 1A
illustrates a plurality of functional blocks (blocks A, B, C and D) located within a larger functional block
10
(at the highest level, functional block
10
can represent the entire integrated circuit). By way of example, a single wire is shown connecting block A
20
and block D
30
. For the purposes of this discussion, the wire is divided into three segments: segment
40
a
is within block A
20
, segment
40
b
runs between block A
20
and block D
30
, and segment
40
c
is within block D
30
.
Blocks A
20
and D
30
(as, well as blocks B and C) are each represented by a timing model. In the prior art, the timing model of the timing arc for block A
20
incorporates the “raw” layout parasitic data (e.g., R and C) for that block, including that for wire segment
40
a.
In other words, the layout parasitics are considered when generating the timing arcs for block A
20
. The layout parasitics are modeled linearly and incorporated into the timing arc model of block A
20
. Similarly, the timing model for block D
30
incorporates the effects of the layout parasitic data for that block, including that for wire segment
40
c.
As described above, in a hierarchical timing analysis, these timing models are integrated with the other timing models in a circuit analyzer in order to perform the timing analysis at the next highest level (that is, at the level of functional block
10
). In the prior art, wire segment
40
b
is incorporated into the timing analysis at the level of functional block
10
.
The prior art is problematic when the lower level models are used in an analysis at a higher level in the hierarchical timing analysis, because the higher level timing analysis has its own layout parasitic data. As a result, the wire from block A
20
to block D
30
inherently has a dual modeling. That is, the parts of the wire inside the lower level timing models (e.g., segments
40
a
and
40
c
) are represented linearly (using, for example, a lookup table) while the part of the wire in the higher level timing model, outside the lower level models (e.g., segment
40
b
), is represented nonlinearly using raw layout parasitic data. Adding the linear representations and the nonlinear representation can yield inaccurate results; this loss of accuracy is particularly acute at lower levels in the timing analysis, where the circuit size is smaller. Thus, a disadvantage to the prior art is that the duality in the models, with regard to the different treatment of layout parasitic data inside and outside of the timing models, can reduce accuracy in the timing analysis.
Prior Art
FIG. 1B
illustrates an exemplary higher level block (e.g., circuit
50
) which includes a lower level block (e.g., subcircuit
55
) that is at the transistor level of a circuit. Layout parasitic data are represented by a combination of resistors and capacitors (e.g.,
60
a
,
60
b
,
61
a
,
61
b
,
62
a
,
62
b
,
63
a
,
63
b
,
64
a
and
64
b
). For an analysis at the transistor level, inverter
56
drives the gates of transistors
57
,
58
and
59
through the netlist described by
60
a
,
60
b
,
61
a
,
61
b
,
62
a
,
62
b
,
63
a
,
63
b
,
64
a
and
64
b
. For a hierarchical timing analysis, in the model for subcircuit
55
(represented using dashed lines as model
70
), inverter
56
drives pin
65
through the netlist described by
60
a
and
60
b.
In this case, a netlist inside model
70
is not visible when running the timing analysis for circuit
50
. Instead, the effects of the netlist inside model
70
are incorporated in the model for subcircuit
55
. Thus, the layout parasitics that belong to circuit
50
are analyzed differently than the layout parasitics that belong to model
70
, introducing accuracy problems in the timing analysis.
In addition, when a circuit analyzer is applied at the transistor level of a circuit (that is, at the lowest level in the hierarchy of the timing analysis), a higher level of accuracy is desired for the circuit analysis. Therefore, a reduction in accuracy due to the prior art technique for modeling layout parasitics at the interface pins is particularly undesirable at the transistor level.
Accordingly, a need exists to resolve the modeling duality caused by the treatment of layout parasitic data at a lower level versus a higher level of a hierarchical timing analysis. A need also exists for a device or method that can be utilized at the transistor level. The present invention solves these needs. These and other objects and advantages of the present invention will become clear to those of ordinary skill in the art in light of the following detailed description of the preferred embodiments which are illustrated in the various drawing figures.
DISCLOSURE OF THE INVENTION
The present invention provides a method of generating timing models that addresses the modeling duality caused by the treatment of layout parasitic data at the lower and higher levels in a hierarchical timing analysis. The present invention also prov
Berevoescu Paul
Levitsky Oleg
Bever Hoffman & Harms LLP
Craig Dwin
Harms Jeanette S.
Jones Hugh
Synopsys Inc.
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