Unified memory distributed across multiple nodes in a...

Details Unified memory distributed across multiple nodes in a... Unified memory distributed across multiple nodes in a...

2006-03-07

2006-03-07

Chauhan, Ulka J. (Department: 2671)

Computer graphics processing and selective visual display system

Computer graphic processing system

Plural graphics processors

C345S505000, C712S011000

Reexamination Certificate

active

07009614

ABSTRACT:
A system is described that is broadly directed to a system of integrated circuit components. The system comprises a plurality of nodes that are interconnected by communication links. A random access memory (RAM) is connected to each node. At least one functional unit is integrated into each node, and each functional unit is configured to carry out a predetermined processing function. Finally, each RAM includes a coherency mechanism configured to permit only read access to the RAM by other nodes, the coherency mechanism further configured to permit write access to the RAM only by functional units that are local to the node.

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