Uni-stage delay speculative address decoder

Details Uni-stage delay speculative address decoder Uni-stage delay speculative address decoder

2007-08-14

2007-08-14

Le, Vu A. (Department: 2824)

Static information storage and retrieval

Addressing

C365S230060

Reexamination Certificate

active

11287907

ABSTRACT:
An address decoder. The address decoder includes a plurality of decoder circuits. Each decoder circuit includes a first stage including a first logic circuit having n−1 inputs, the n−1 inputs being a subset of n inputs conveyed to each decoder circuit. Each decoder circuit further includes a second stage having a second and third logic circuits. Both the second and third logic circuits receive an output provided by the first logic circuit. The second logic circuit also receives the other one of the n bits, while the third logic circuit receives its complement. The second and third logic circuits provide second and third outputs, respectively. The address decoder is configured to assert one of a plurality of address selection outputs by asserting one of the second or third outputs of one of the decoder circuits, while de-asserting both the second or third outputs of the other decoder circuits.

REFERENCES:
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patent: 6055203 (2000-04-01), Agarwal et al.
patent: 6586970 (2003-07-01), Jung
International search report application No. PCT/US2006/044303 mailed Mar. 27, 2007.

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