Unerasable programmable read-only memory

Details Unerasable programmable read-only memory Unerasable programmable read-only memory

1991-06-27

1994-08-16

Prenty, Mark V.

Active solid-state devices (e.g., transistors, solid-state diode

With shielding

257660, 257323, 365 53, H01L 2968, H01L 2940, G11C 702

Patent

active

053389697

ABSTRACT:
An unerasable memory cell (10) is formed in the face of a layer (22) of semiconductor of a first conductivity type and includes an erasable read-only memory cell (12) having a first source/drain region (16) and a second source/drain region (18) of a second conductivity type opposite the first conductivity type. First source/drain region (16) is spaced from second source/drain region (18) by a channel area (24). A floating gate conductor (20) is disposed insulatively adjacent channel area (24) and a control gate conductor (22) disposed insulatively adjacent floating gate conductor (20). A heavily doped moat (32) of the second conductivity type laterally surrounds memory cell (12). A load device (14/66) couples moat (32) with first source/drain region (16) of a memory cell (12). A shield (46/56) is provided having a first portion (47/64) spaced from and substantially parallel to the face of semiconductor layer (22) and a second portion (52/62) formed at an angle to the face and coupling the first portion (47/64) with moat (32). Shield (46/56) substantially encloses memory cell (12).

REFERENCES:
patent: 4758984 (1988-07-01), Yoshida
patent: 4805138 (1989-02-01), McElroy et al.
patent: 5050123 (1991-09-01), Castro
patent: 5086410 (1992-02-01), Bergemont

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