Undershoot eliminator circuit and method for synchronous...

Electric power conversion systems – Current conversion – Including d.c.-a.c.-d.c. converter

Reexamination Certificate

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C363S021140, C363S127000

Reexamination Certificate

active

07054168

ABSTRACT:
An undershoot eliminator circuit is disclosed that avoids the occurrence of a negative undershoot that typically happens when an isolated DC-DC converter with a secondary side synchronous driver that is turned off. The undershoot eliminator circuit functions to discharge an energy storage element in an auxiliary supply on said secondary side of said converter. The circuit includes a clamp transistor having a gate terminal, a source terminal, and a drain terminal, the drain terminal of the transistor connected to said storage element, the source terminal of the transistor connecting to the output of the converter; means for trapping charge on the gate terminal of the clamp transistor while said converter is on; and means for coupling the voltage on the output of the converter to the gate terminal, such that, when said converter goes off and its output voltage begins to drop, the trapped charge causes the gate-to-source voltage of the clamp transistor to increase until the gate of the transistor is sufficiently saturated to cause it to turn on for a sufficient time to discharge the storage element. The undershoot eliminator circuit preferably employs a capacitor for trapping a charge on the gate terminal of the clamp transistor. The storage capacitor is quickly discharged to avoid a negative undershoot from occurring when the DC/DC power converter is turned off.

REFERENCES:
patent: 5343383 (1994-08-01), Shinada et al.
patent: 5724235 (1998-03-01), Shimamori et al.
patent: 6813166 (2004-11-01), Chang et al.
patent: 6882548 (2005-04-01), Jacobs et al.

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