Underfill applications using film technology

Details Underfill applications using film technology Underfill applications using film technology

2001-03-15

2003-02-04

Sherry, Michael (Department: 2829)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Encapsulating

C425S127000

Reexamination Certificate

active

06514797

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to assembly and manufacture of semiconductor device packages and, more particularly, to a new technique for assembling semiconductor device packages using film technology.
BACKGROUND
Semiconductor devices, for example dynamic random access memory (DRAM) devices, are shrinking in the sense that smaller devices are being manufactured that are able to handle larger volumes of data at faster data transfer rates. As a result, semiconductor manufacturers are moving toward chip-scale packages (CSP) for semiconductor components which have a small size and fine pitch wiring.
One exemplary CSP uses a chip-on-board (COB) construction whereby a semiconductor component, such as an integrated circuit (IC) chip, is attached to a base material, such as a substrate, with a conductive adhesive material. The conductive adhesive material is interposed between and bonds the IC chip and the substrate at specified locations in order to permit electrical connections between the chip and substrate. In addition, electrical traces or wiring patterns may be included in or on the substrate to permit the IC chip to connect with other external devices, for example a printed circuit board (PCB).
For example, in an exemplary COB package, solder balls may be used to bond and electrically connect the IC chip and the substrate. The solder balls may be placed at specified locations on the IC chip and/or substrate in order to form the desired electrical connections. The substrate may be attached by leads, solder balls or other electrical connectors to a PCB for use in an electronic system. Similar structures may be used in other types of semiconductor packages, such as board-on-chip ball grid array (BOC-BGA), flip chip, wafer level CSP (WLCSP), and thin small outline packages (TSOP).
Because semiconductor manufacturers are continually under pressure to reduce the size of their packages, it is generally desirable to use a small amount of adhesive between the IC chip and the substrate. Solder bumps (very small solder balls) may be used to bond the IC chip and the substrate, but the space between the IC chip and substrate is not completely filled with the adhesive, leaving a small amount of empty space adjacent the solder bumps. The resulting structure thus resembles a “sandwich,” with solder bumps and empty space interposed between the IC chip and substrate. The empty space is usually filled with an “encapsulant,” or a mold compound to increase the reliability of the package. The process of filling the empty space with the encapsulant is known as “underfill” of IC packages.
A problem arises in forming packages of small size, in that the gap between the IC chip and the substrate may be very small, such that the empty space may not be filled properly even when the encapsulant is applied to fill the gap using high pressure or vacuum techniques. An unfilled space between the IC chip and substrate is commonly known as a “void” and may lead to package reliability problems such as delamination or cracks. For example, the manufacturing specification for the thin small outline package (TSOP) does not allow voids larger than 10 mils to be present. However, for other packages the permissible void specification may be even more restrictive depending on the package characteristics, such as package design, mold height, and materials used. Post-encapsulation treatment may assist in eliminating the voids, but may increase the cycle time and production cost of the package.
Therefore, there is a strong need and desire for a technique for underfilling IC packages that substantially eliminates voids without significantly increasing the cycle time or production cost of the semiconductor packaging process.
SUMMARY
The invention provides a method and apparatus for producing a semiconductor package. The invention uses a thin release film placed over assembled components in a mold cavity, the assembled components including an integrated circuit (IC) chip, a substrate, and solder balls or bumps interposed between the chip and substrate. The release film is drawn down over and/or pressed against the assembled components assisted by at least one vacuum source, and pressure applied over the film using air or mechanical means. The release film thus envelops the assembled components and creates an airtight seal around at least three sides for initially confining the flow of encapsulant into the area between the chip and substrate. A mold compound or encapsulant is then flowed into the empty space between the chip and substrate, defined by vacuum and the airtight seal created by the film. The release film is then pulled up and away from the assembled components, permitting encapsulant to then flow into the remainder of the mold cavity.
In one embodiment, the mold cavity is formed to produce bare die semiconductor packages, in which, after the release film is pulled up, the encapsulant is permitted to flow around the perimeter of the IC chip but not over the top of the IC chip to form the semiconductor package.
In another embodiment, the mold cavity is formed for overmold semiconductor packages, in which, after the release film is pulled up, the encapsulant is permitted to flow around the perimeter and over the top of the IC chip to form the semiconductor package.


REFERENCES:
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patent: 6048656 (2000-04-01), Akram et al.
patent: 6101790 (2000-08-01), Mori et al.
patent: 6149010 (2000-11-01), Tanaka et al.
patent: 0 458 423 (1991-11-01), None

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