Undercut process with isotropic plasma etching at package level

Details Undercut process with isotropic plasma etching at package level Undercut process with isotropic plasma etching at package level

1997-05-20

2004-02-03

Kunemund, Robert (Department: 1765)

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

C438S051000, C438S057000, C438S067000, C438S107000, C438S110000

Reexamination Certificate

active

06686291

ABSTRACT:

CROSS REFERENCE TO RELATED APPLICATIONS AND PATENTS
SERIAL NO./
DATE FILED/
PATENT NO.
TITLE
DATE ISSUED
5,597,767
Separation of Wafer into Die with
ISSUED
Wafer-Level Processing
01/28/97
5,610,438
Micro-Mechanical Device
ISSUED
03/11/97
60/015,107
Manufacturing Process of Digital
04/11/96
Micromirror Device
60/016,732
Method of Reducing Wafer Particles
05/02/96
After Partial Saw
FIELD OF THE INVENTION
The present invention relates to the protection of active sites on a semiconductive wafer which is sawed into individual active-site-bearing chips, and more particularly to a method of protecting, during and after sawing, active sites such as micromechanical devices from debris and deleterious substances which are produced by, or are used in, such sawing.
BACKGROUND OF THE INVENTION
Numerous processes are known for producing plural arrays of active sites in and on a first surface of a semiconductor wafer. Each active site may comprise a micromechanical device having deflectable elements such as a digital micromirror device (DMD) such as that manufactured by Texas Instruments of Dallas Tex., but could also include accelerometers, sensors etc. The wafer is ultimately separated into a plurality of individual chips, also known as dies or bars, each of which includes one of the active site arrays, the array having a “top” surface comprising a portion of what was formerly the wafer's first surface. Each active site array has associated therewith one or more bond pads on its top surface. The bond pads are rendered selectively electrically continuous with the active sites, typically by depositing or otherwise forming them on top of, and in electrical contact with, conductors formed on the wafer. Some of the same steps used to produce the active sites may also produce the conductors, which are themselves electrically continuous with the active sites.
The separation of the wafer into individual chips is effected by an operation which may be referred to as “complete sawing”, or “partial sawing” followed by a “breaking” process. Sawing separates the wafer along lines or paths commonly referred to as “streets” extending between locations whereat adjacent active site arrays reside or will ultimately reside.
Sawing, which typically involves mechanical abrasion and erosion of the wafer, may be achieved by a number of techniques, including those which utilize rotating saw blades and vibrating tips. Accordingly, the act of sawing the wafer itself produces substantial debris which includes small pieces of the wafer including oxide particles from a CMOS layer, and possibly small pieces of the saw blade or vibrating tip. Sawing is also typically accompanied by cooling/lubricating fluids and other substances which prevent the saw blade or tip from damaging the wafer and which prolong the life of the saw blade or tip.
The debris resulting from and the substances used in sawing can degrade the performance of or render inoperative the active sites, particularly moving parts of a micromechanical device. If the active sites include a spatial light modulator (“SLM”), such as that known as a deflectable mirror device or a digital micromirror device (collectively “DMD”), each active site may be even more sensitive to the effects or presence of the debris and fluids resulting from and used in sawing.
A DMD is a multilayered micromechanical structure formed on a wafer, which includes a light-reflective beam or similar mechanical member. An example of a DMD is disclosed in commonly assigned U.S. Pat. No. 5,061,049 entitled “Spatial Light Modulator and Method”, the teachings incorporated herein by reference. An area or linear array of beams are associated with an active site and are so mounted to, or hinged from, the structure formed on the wafer as to be deflectable or movable between a normal position and other positions. Deflection of the beam may be achieved by electrostatically attracting the beam toward (or to) an underlying adjacent electrode which is at a different electrical potential from that of the beam. Deflection of the beam stores energy in its mount or hinge, which stored energy tends to return the beam to its normal position absent the electrical potential. Movement of the beam, which may be binary or analog, is controlled by the circuit components of the active site associated with the beam and functioning as an addressing circuit. Deflection of the beam is facilitated by an undercut well which underlies the beam. The well is formed by appropriate etching of one of the spacer layers of material deposited on the wafer, typically comprising photoresist.
In use, an array or matrix of DMD's is arranged to receive light from a source. The received light which is incident on the reflective beams is selectively reflected or not reflected onto a viewing surface, such as a screen, depending on the position of the beams. Such reflected light is directed by each beam onto the viewing surface in only one selected position, which may be the normal position or one of the other deflected positions. In all other positions of each beam other than the selected position, the incident, reflected light is directed in such a way that it does not fall on the viewing surface, such as to a light absorber. Appropriate energization of the circuit components of the addressing circuit associated with each beam of each active site in the array or matrix permits the beam-reflected light on the viewing surface to be presented as a rasterized array of pixels (as in a typical television) or as a scanning line of pixels (as in a line printer). Thus, the beam of each active site is or acts as a pixel.
Because a DMD includes circuit components as well as a microminiature deflectable beam, it is especially sensitive to debris resulting from sawing the wafer and to the fluids and other substances used to facilitate sawing. Such debris can enter the undercut well and prevent deflection of the beam. In one technique, formation of the circuit components of the active sites and etching or other steps which define the beams are followed by the deposit of a protective layer thereon. Sawing of the wafer to separate the arrays then proceeds, the protective layer preventing the sawing operation from damaging the circuit components and the etch-defined beams. After sawing is completed, but while still in wafer form, the protective layer is removed and the undercut wells are then formed under each beam by plasma etching the spacer layer. Formation of the wells at this time reduces the sawing-related debris and substances from entering the wells. However, automatic pick-and-place equipment and other automatic or human handling can still generate damaging particles until the DMD device is secured to and finally hermetically sealed in the package.
One object of the present invention is the provision of a method of protecting each active site in plural active site arrays on a fully processed semiconductor wafer, particularly active sites which include a DMD SLM or other micromachine, so that beam-defining etching and well formation may all be carried out with reduced particles inhibiting operation of the device before it is hermetically sealed in a package.
In commonly assigned U.S. Pat. No. 5,389,182 to Mignardi entitled “Use of a Saw Frame with Tape as a Substrate Carrier for Wafer Level Backend Processing”, there is disclosed a method for processing a wafer containing microelectronic mechanical devices. The method allows all fabrication and test steps to be performed in wafer form upon a dicing tape, whereby the wafer is completely sawn to separate the devices from one another, but wherein the devices are left on the dicing tape during the remaining fabrication steps including device testing and undercutting of the spacer layer beneath the mirrors.
In commonly assigned U.S. Pat. No. 5,393,706 to Mignardi, et al entitled “Integrated Partial Sawing Process”, there is disclosed a process for partially sawing streets on a semiconductor wafer, and then covering the streets with a protective material. After the wafer is broken to separate

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