Under bump metallization structure of a semiconductor wafer

Details Under bump metallization structure of a semiconductor wafer Under bump metallization structure of a semiconductor wafer

2005-08-16

2005-08-16

Cao, Phat X. (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Bump leads

C257S738000, C438S613000

Reexamination Certificate

active

06930389

ABSTRACT:
An under bump metallurgy structure is applicable to be disposed above the wafer and on the bonding pads of the wafer. The wafer comprises a passivation layer and an under bump metallurgy structure. The passivation layer exposes the wafer pads, and the under bump metallurgy structure including an adhesive layer, a first barrier layer, a wetting layer and a second barrier layer are sequentially formed on the bonding pads. Specifically, the material of the second barrier mainly includes lead.

REFERENCES:
patent: 2003/0189260 (2003-10-01), Tong et al.
patent: 2004/0238955 (2004-12-01), Homma et al.

Affiliated with

Also associated with

Rating

Under bump metallization structure of a semiconductor wafer does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Under bump metallization structure of a semiconductor wafer, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Under bump metallization structure of a semiconductor wafer will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3476102