Unbalanced sense circuit

Electrical transmission or interconnection systems – Personnel safety or limit control features – Interlock

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Details

37238, 307279, 307288, 307DIG3, 365184, 365205, H03K 520, H03K 3286, G11C 700, G11C 1140

Patent

active

041140559

ABSTRACT:
The sense circuit includes first and second inverters connected at their inputs to a signal input node and a reference node, respectively. The inverters are selectively biased to different quiescent points for charging the signal input node and the reference node to different quiescent voltage levels. Signals applied to the signal input and reference nodes cause the potential at these nodes to vary from their quiescent values. The inverters are selectively cross-coupled to form a flip flop whose binary value is determined by the outputs of the inverters. For the same value of signals applied to the two nodes the flip flop is set to the state dictated by the initial voltage offset due to the difference in the quiescent points of the inverters.

REFERENCES:
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patent: 3879621 (1975-04-01), Cavaliere et al.
patent: 3895360 (1975-07-01), Cricchi et al.
patent: 3902082 (1975-08-01), Proebsting et al.
patent: 3983543 (1976-09-01), Cordaro
patent: 3983544 (1976-09-01), Dennison et al.
patent: 3983545 (1976-09-01), Cordaro
patent: 3992704 (1976-11-01), Kantz
Lohman, "Applications of MOS FETs in Microelectronics"; SCP and Solid-State Technology, (pub.); pp. 23-29; 3/1966.
Krick, IBM Tech. Discl. Bull.; vol. 17, No. 6, pp. 1811-1813; 11/1974.

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