Ultraviolet erasable nonvolatile semiconductor device

Details Ultraviolet erasable nonvolatile semiconductor device Ultraviolet erasable nonvolatile semiconductor device

1988-07-25

1990-07-24

Carroll, J.

357 6, 357 2314, 357 54, H01L 4902, H01L 2978, H01L 2934

Patent

active

049438360

ABSTRACT:
An ultraviolet erasable nonvolatile seimconductor device has a floating gate, a conrol gate, and a gate insulating layer interlayered between the floating gate and the control gate. The interlayered gate insulating layer consists of three layers, a first silicon oxide layer, a silicon nitride layer layered on the first silicon oxide layer, and a second silicon oxide layer. The second silicon oxide layer as the top layer of the three-layered gate insulating layer is 30 .ANG. or less in thickness.

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patent: 4495693 (1985-01-01), Iwahashi et al.
patent: 4577390 (1986-03-01), Haken
patent: 4630086 (1986-12-01), Sato et al.
patent: 4665426 (1987-11-01), Allen et al.
S. Mori et al., "Poly-Oxide/Nitride/Oxide Structures for Highly Reliable EPROM Cells", 1984 Symposium on VLSI Technology Digest of Technical Papers, (Sep. 1984), pp. 40-41.
S. Mori et al., "Reliable CVD Inter-Polydielectrics for Advanced E & EEPROM", 1985 Symposium on VLSI Technology Digest of Technical Papers, (May 1985), pp. 16-17.

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