Ultrathin electronics using stacked layers and interconnect vias

Details Ultrathin electronics using stacked layers and interconnect vias Ultrathin electronics using stacked layers and interconnect vias

1997-02-26

2000-12-26

Hardy, David

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

For plural devices

257700, 257723, H01L 23485

Patent

active

061664383

ABSTRACT:
An integrated circuit and associated method for reducing total signal propagation delay as well as power consumption and thermal dissipation. The integrated circuit comprises a plurality of active layers coupled together in close proximity. In order to produce the integrated circuit, at least two active layers are removed from their respective substrate after integrated circuit processing. Some of the methods that may be used include Silicon on Insulator ("SOI") and epitaxial etch stop ("EES") processes. After removal of the active layers, at least one via is implemented on a bottom surface of each active layer in order to establish a mechanical and electrical connection between the via and its associated metal interconnects. Thereafter, the active layers are coupled together by ultrasonic welding or through nitride lamination using Titanium Nitride for conductive regions and Silicon Nitride for insulative regions.

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