Ultrasonic delay line matrix switch check system

Details Ultrasonic delay line matrix switch check system Ultrasonic delay line matrix switch check system

1985-07-26

1987-06-23

Howell, Kyle L.

Surgery

Truss

Pad

73626, A61B 1000

Patent

active

046745165

DESCRIPTION:

BRIEF SUMMARY
TECHNICAL FIELD

This invention relates to an ultrasound diagnostic equipment with a matrix switch checking means.


BACKGROUND ART

In an ultrasound diagnostic equipment, a delay line with more than one tap is used. Thus, a signal received by each transducer is supplied to the specified tap on the delay line to output the synthesized receive signal obtained by adding each signal having the respective specified delay time from one end of this delay line. Delay time of each signal is changed by delay-line tap selection to change the received wave beam direction and focus. Delay-line tap selection is made using a matrix switch to enable any one of the received signals to connect to any one of the taps.
As aforementioned, the matrix switch becomes the principal part of the ultrasound diagnostic equipment. On the other hand, the matrix switch is provided with several thousand switching elements.
So far, this matrix switch has been checked by means of a complex checking device as disclosed in Japanese Patent Provisional Publication No. 44364/82. Thus, the matrix switch has been checked only by the use of a special checking device.


DISCLOSURE OF THE INVENTION

The purpose of this invention is to provide an ultrasound diagnostic equipment with a matrix switch checking means configured in a combined use with means commonly furnished to said equipment, thus removing the aforementioned disadvantage.
For the accomplishment of this purpose, the device in this invention has a built-in test sequencer, whereby taps on the delay line are selected in order from one end of said taps for each channel of the matrix switch to input a checking signal to that channel from an ultrasound transducer drive circuit each time the taps are selected; as a result a signal obtained from the delay-line output terminals is shown on a display screen of a display device as a mimic echo signal to determine the presence or absence of any fault of switching elements in the relevant channel of the matrix switch based on a mimic echo image pattern shown on the display device.


BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a block diagram showing the configuration of the embodiment of this invention;
FIG. 2 shows waveform diagrams showing signal waveforms at the respective portions in FIG. 1; and
FIG. 3, 4, 5 and 6 show examples of displays on CRT as test results.
FIG. 7 shows a circuit diagram wherein one switching element of the matrix switch continues closing due to its fault.
FIG. 8 shows waveform diagrams of pulse waveforms generated under the fault occurring when one switching element of the matrix switch continues closing.
FIG. 9 shows a block diagram showing the detailed configuration of the send signal delay and channel select circuit.


BEST MODE FOR CARRYING OUT THE INVENTION

In the following, the embodiment in this invention is described by referring to the figures in the drawing.
Referring to FIG. 1, the equipment in this invention consists of a send signal delay & channel select circuit 1, send amplifiers 21 to 2n, transducers 31 to 3n, receive amplifiers 41 to 4n, matrix switch 5, delay line with taps 6, detector amplifier 7, analog-to-digital converter (hereinafter called A/D converter) 8, video memory 9, digital-to-analog converter (hereinafter called D/A converter) 10, image display device (hereinafter called CRT) 11, trigger generator 12, test sequencer 13, scan sequencer 14, switch circuit 15, and address controller 16.
One of output pulses from the trigger generator 12 is fed to the send signal delay & channel select circuit 1 as an input signal. Each of the outputs (n in number) of the send signal delay & channel select circuit 1 connects to each of the inputs (n in number) of the send amplifiers 21 to 2n, while each of the outputs (n in number) of the send amplifiers 21 to 2n connects to each of the inputs (n in number) of the receive amplifiers 41 to 4n. On the other hand, each of the outputs (n in number) of the receive amplifiers 41 to 4n connects to each of the receive signal input lines (n in number) of the matrix

REFERENCES:
patent: 4373323 (1983-02-01), Takemura et al.
patent: 4423737 (1984-01-01), Yano et al.
patent: 4528854 (1985-07-01), Shimazahi
patent: 4544926 (1985-11-01), Shirasaha

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