Coded data generation or conversion – Analog to or from digital conversion – Differential encoder and/or decoder
Reexamination Certificate
2001-04-18
2002-12-10
JeanPierre, Peguy (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Differential encoder and/or decoder
C341S144000
Reexamination Certificate
active
06492925
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to electronic circuits and systems. More specifically, the present invention relates to analog to digital signal processors for use in communications receivers and radars.
2. Description of the Related Art
Radio frequency receivers should process the input signal as quickly as possible, i.e. as close to the antenna as possible, in order to obtain a high signal to noise ratio. Receivers generally have several stages of down-conversion, converting the RF (radio frequency) input signal to lower intermediate frequencies (IFs). The circuitry used to down-convert the signal, however, is subject to a number of limitations, including noise, drift, and dynamic range issues. It is therefore desirable to convert the signal to digital as close as possible to the antenna.
Currently, however, digital signal processing cannot be performed at the high (RF) frequencies received by the antenna. Digital signal processing is usually performed after several stages of down-conversion, at lower IFs (baseband to 100 MHz).
A digital signal processor is needed which can process the signal without as many intermediate stages of down-conversion, preferably at the first IF stage. In a typical radar system, for example, the first IF stage is upwards of 5 GHz. Currently, sigma-delta analog to digital converters can be used to process frequencies up to only 2 GHz. Sigma-delta converters higher than 2 GHz are not possible using currently available technology. Furthermore, these sigma-delta converters are conventionally narrow-band frequency specific integrated circuits with internally tuned electrical elements, such that different sigma-delta converters would need to be produced for use at different frequencies, dictating specific individual devices for each application. It would be more cost effective to produce a general purpose A/D converter which could be used for a wide range of frequencies.
Hence, a need exists in the art for an analog to digital signal processor designed for use at ultra-high frequencies greater than 2 GHz.
SUMMARY OF THE INVENTION
The need in the art is addressed by the ultra-wide band general purpose analog to digital (A/D) signal processor of the present invention. The processor includes a first circuit for shifting a frequency of an input signal, a second circuit for processing the input signal, and a third circuit for selectively bypassing the first circuit whereby the input signal is provided directly to the second circuit in a first mode of operation and to the second circuit via the first circuit in a second mode of operation.
In the illustrative embodiment, the first circuit is a mixer with a specific normalized mixing ratio of 0.8 to 0.9. The second circuit is a sigma-delta analog-to-digital converter. The third circuit is a switch for passing the input signal directly to the second circuit if the input is 20 MHz to 2 GHz or for passing the input signal to the first circuit if the input is 2 GHz to 5 GHz. In the preferred embodiment, the switch, the mixer, and the sigma-delta converter are disposed on a single application specific integrated circuit (ASIC) substrate.
In the illustrative embodiment, the processor further includes a range selector for controlling the switch, a local oscillator connected to the mixer, a first filter connected between the input signal and the second circuit in the first mode of operation or between the first circuit and the second circuit in the second mode of operation, a second filter connected between the input signal and the second circuit in the second mode of operation, a noise-canceling tuning element connected to the sigma-delta converter, and a clock connected to the sigma-delta converter. In the preferred embodiment, these elements are located external to the integrated circuit.
This implementation operates by taking advantage of the maximum frequency (2 GHz) achievable by today's state of the art sigma-delta technology, in combination with a specific superheterodyning frequency scheme, allowing almost spurious-free performance for the entire composite frequency range of interest (20 MHz to 5 GHz). Furthermore, the processor as described above does not require any internal tuning, as conventional sigma-delta converters do. Preconditioning and tuned noise canceling can be performed external to the general purpose integrated chip. The external elements can be easily adapted to various input frequencies, allowing the general purpose processor to be used as an AID converter in a variety to applications.
REFERENCES:
patent: 6034990 (2000-03-01), Kang
patent: 6236674 (2001-05-01), Morelli et al.
patent: 6289059 (2001-09-01), Yamaguchi et al.
patent: 6329260 (2001-12-01), DeJong et al.
Alkov Leonard A.
Jean-Pierre Peguy
Lauture Joseph
Lenzen, Jr. Glenn H.
Raufer Colin M.
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