Ultra-thin wafer level stack packaging method

Details Ultra-thin wafer level stack packaging method Ultra-thin wafer level stack packaging method

2007-03-20

2007-03-20

Parekh, Nitin (Department: 2811)

Semiconductor device manufacturing: process

Semiconductor substrate dicing

With attachment to temporary support or carrier

C438S109000, C438S110000, C438S118000, C257S777000, C257S458000, C257SE21599, C257SE21596, C257S686000

Reexamination Certificate

active

10906136

ABSTRACT:
A method of forming an ultra-thin wafer level stack package and structure thereof are provided. The method includes providing a first wafer having a plurality of base chips thereon, selectively binding the first wafer to a second substrate, lapping the first wafer to reduce its thickness, dicing the lapped first wafer, bonding a plurality stack chips to each base chip and packaging the base chip with the bonded stack chips to form an IC package. Thus, each IC package comprises at least a base chip and a stack chip. The IC package has a size almost identical to the base chip and a thickness a little larger than the combined thickness of the base chip and the stack chip. If a known good die inspection of the base chips and stack chips are carried out prior to wafer level packaging, overall yield of the IC package is increased.

REFERENCES:
patent: 5000811 (1991-03-01), Campanelli
patent: 5547906 (1996-08-01), Badehi
patent: 6849523 (2005-02-01), Chao et al.
patent: 2006/0172510 (2006-08-01), Connell et al.

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