Ultra-thin outline package for integrated circuit

Details Ultra-thin outline package for integrated circuit Ultra-thin outline package for integrated circuit

1999-10-14

2003-02-11

Wu, Daniel J. (Department: 2632)

Communications: electrical

Condition responsive indicating system

Specific condition

C340S572800, C257S698000, C257S774000

Reexamination Certificate

active

06518885

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to integrated circuits, and more particularly, to a method and system for packaging integrated circuits to provide an ultra-thin outline package.
2. Description of Related Art
In the semiconductor packaging industry, it is known to assemble a semiconductor chip into a plastic package having a lead frame that provides electrical connections to the chip through the package material. These chip packages may be connected to a printed circuit board using various techniques, such as surface mounting. A surface mounted package has leads configured to lie flat on top of conductive pads provided on the printed circuit board. The leads are then soldered to the conductive pads. A conductive solder paste may be used to temporarily hold the chip package in place while the printed circuit board and chip are placed into an oven. The heat from the oven then causes the solder paste to flow and form an electrical connection between the leads and pads upon subsequent cooling of the solder paste.
It is increasingly desirable to reduce the profile of the semiconductor package above the printed circuit board so that electronic systems can be incorporated into compact devices and products. Various low-profile format semiconductor packages have been developed, such as thin small outline package (TSOP), thin shrink small outline package (TSSOP), and mini small outline package (MSOP). The smallest of these package formats, MSOP, has a profile of one millimeter. A drawback of these low profile package formats is they are not conducive to rapid prototyping of chip designs where the footprint or size of the semiconductor chip changes and does not fit an existing leadframe. With each new semiconductor chip design, an associated lead frame and injection mold for the plastic package must be adapted specifically.
It is also known to attach semiconductor chips to a circuit board or substrate directly without using a plastic package or lead frame. Instead, the chip is bonded directly to the surface of the substrate and wire bonds are used to join conductive pads of the chip to corresponding conductive traces of the substrate. Alternatively, the chip can be flipped upside down (“flip-chip”) and the conductive pads of the chip directly aligned to the conductive pads of the substrate. Thereafter, the chip may be encapsulated in an epoxy resin (“glob-top”) to provide environmental protection of the chip and electrical connections. While these methods are desirable in reducing the profile of the chip above the substrate, they have significant drawbacks as well. The wire bonds require a minimum vertical (i.e., relative to the plane of the chip) loop height that translates into increased profile of the chip. A drawback of flip-chip attachment is the difficulty of aligning the chip to the conductive traces of the substrate, and high precision optical alignment systems are generally necessary to achieve proper alignment.
One application for low-profile chip packaging is in the fabrication of radio frequency (RF) and radio frequency identification (RFID) transponders. The use of RF transponders (also known as RF tags) has grown in prominence as a way to track data regarding an object on which an RF transponder is affixed. An RF transponder may comprise a semiconductor chip and an antenna mounted to a substrate. An RF interrogator containing a transmitter-receiver unit is used to query an RF transponder that may be at a distance from the interrogator. The RF transponder detects the interrogating signal and transmits a response signal containing encoded data back to the interrogator. RF transponders may either be “battery-powered,” in which they include an internal power source (i.e., battery), or “field-powered,” in which they do not include a battery and derive their energy entirely from the interrogating signal provided by the RF interrogator. The battery powered RF transponders generally have a greater operating range than field powered transponders, but have the associated disadvantage of greater bulk due to the inclusion of the battery. An RFID transponder further includes a semiconductor memory that can store identifying information regarding an object to which the RFID transponder is affixed. RF and RFID systems are used in numerous applications, such as inventory management, security access, personnel identification, factory automation, automotive toll debiting, and vehicle identification, to name just a few. Since it is desirable to include RF and RFID systems in compact applications, such as in a printed label or card stock, there is a critical need for very low-profile packaging for the semiconductor chip.
Accordingly, it would be very desirable to provide a chip packaging method and apparatus having a profile less than the aforementioned packaging and chip attachment techniques. More specifically, it would be very desirable to provide a very low-profile chip packaging method for use in fabricating RF or RFID transponders.
SUMMARY OF THE INVENTION
The present invention is directed to an ultra-thin outline package for integrated circuits that is much smaller than conventional chip packaging structures. The ultra-thin outline package is particularly useful in fabricating RF or RFID transponders.
In an embodiment of the invention, the ultra-thin outline package includes a substrate having an aperture. At least one conductive trace that includes upper and lower portions is disposed on respective upper and lower surfaces of the substrate. The substrate further comprises at least one via electrically connecting the conductive trace portions together. An integrated circuit is disposed in the aperture and is operatively coupled to the upper portion of the conductive trace. An encapsulant is provided in the aperture substantially covering the integrated circuit. The lower portion of the conductive trace is adapted for coupling of the ultra-thin outline package to a secondary substrate using conventional surface mounting techniques. The via connecting the upper and lower trace portions may be disposed either on at least one edge surface of the aperture or on at least one edge surface of the substrate. At least one wire bond electrically couples the integrated circuit to the conductive trace, and the encapsulant covers the integrated circuit and the wire bond. Using printed circuit board material for the substrate, the ultra-thin outline package achieves a vertical profile of approximately 0.3 to 0.375 mm (or 12 to 15 mils).
An alternative embodiment of the ultra-thin outline package comprises a substrate having at least one hole extending therethrough. At least one conductive trace is disposed on a lower surface of the substrate at least partially blocking the hole. An integrated circuit is disposed on the substrate and is operatively coupled to the conductive trace through the hole. An encapsulant substantially covers the integrated circuit. The conductive trace is adapted for coupling of the ultra-thin outline package to a secondary substrate using conventional surface mounting techniques. At least one wire bond electrically connects the integrated circuit to the conductive trace, and the encapsulant covers the integrated circuit and the wire bond.
The ultra-thin outline package may be used to fabricate a radio frequency (RF) transponder. The transponder includes a secondary substrate having an antenna disposed on a surface thereof. The ultra-thin outline package may be surface mounted on the secondary substrate in electrical connection with said antenna.
A more complete understanding of the ultra-thin outline package for integrated circuits will be afforded to those skilled in the art, as well as a realization of additional advantages and objects thereof, by a consideration of the following detailed description of the preferred embodiment. Reference will be made to the appended sheets of drawings that will first be described briefly.


REFERENCES:
patent: 6013948 (2000-01-01), Akram et al.
patent: 6100804 (2000-08-01), Brady

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