Electricity: electrical systems and devices – Electrostatic capacitors – Fixed capacitor
Reexamination Certificate
1998-03-04
2001-11-27
Dinkins, Anthony (Department: 2831)
Electricity: electrical systems and devices
Electrostatic capacitors
Fixed capacitor
C361S306300, C361S311000, C361S301300
Reexamination Certificate
active
06324048
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates generally to small electronic components adapted to be mounted on a larger circuit board. More particularly, the invention relates to an ultra-small capacitor array for use in a variety of applications.
For some time, the design of various electronic components has been driven by a general industry trend toward miniaturization. In this regard, a need exists for ever smaller electronic components having exceptional operating characteristics. For example, some applications may require a very small capacitor array wherein each of the individual capacitors has a relatively large capacitance value.
Consider a device specifying an exterior size of no greater than 0.50 mils and 0.55 mils in respective width and length dimensions, while providing an array of three capacitors each having a capacitance of at least 560 picofarads. It is very difficult in such a small component to provide multiple capacitors having the desired capacitance value. Adequate termination structures for connection of the device to external circuitry must also be provided.
SUMMARY OF THE INVENTION
The present invention recognizes various disadvantages of prior art constructions and methods. Accordingly, it is an object of the present invention to provide a novel electronic component.
It is a further object of the present invention to provide a novel capacitor array of ultra-small dimensions.
It is a further object of the present invention to provide a novel capacitor array wherein each of the individual capacitors has a relatively large capacitance value.
It is a still further object of the present invention to provide a novel thin-film capacitor device.
It is an additional object of the present invention to provide a method of manufacturing a thin film capacitor array.
Some of these objects are achieved by a miniature capacitor device for inverted mounting to a predetermined surface. The device comprises a substrate, such as silicon, glass or Al
2
O
3
. A first conductive layer is disposed on the substrate. The first conductive layer defines at least one first capacitor plate and a first terminal structure adjacent thereto. In addition, a dielectric layer is disposed on the first capacitor plate. A second conductive layer defines at least one second capacitor plate and a second terminal structure adjacent thereto. The second capacitor plate is disposed on the dielectric layer in opposition to the first capacitor plate. It will often be desirable to also provide an encapsulate material disposed over layers on the substrate. The encapsulate material is defined to expose the first and second terminal structures.
The dielectric material may preferably have a dielectric constant of at least about 100. Often, the dielectric constant may exceed 500, with a dielectric constant of 1100 being utilized in some exemplary embodiments. The dielectric material may comprises a lead-based dielectric material such as a PZT material. Such a dielectric layer may have a thickness of no greater than approximately 1.0 &mgr;m.
The first conductive layer may comprise at least three first capacitor plates. In this case, the second conductive layer comprises at least three second capacitor plates respectively opposed thereto. The second conductive layer may further define a respective second terminal structure disposed adjacent to each of the second capacitor plates.
Other objects of the invention are achieved by a miniature capacitor array having a plurality of capacitor devices in a single package. The device comprises a substrate having a first conductive layer disposed thereon. The first conductive layer defines a plurality of first capacitor plates. A dielectric layer is disposed on the plurality of first capacitor plates. A second conductive layer defines a plurality of second capacitor plates disposed on the dielectric layer in opposition to respective of the first capacitor plates. The second conductive layer further defines respective terminal structures adjacent to each of the second capacitor plates. It will often be desirable to provide an encapsulate material disposed over layers on the substrate. The encapsulate material is defined to expose the terminal structures.
The first conductive layer may comprise at least three first capacitor plates. The second conductive layer may comprise at least three second capacitor plates respectively opposed thereto.
In some exemplary embodiments, the top surface of the substrate has an area of no greater than approximately 2750 square mils. Each of the capacitor devices may be advantageously located between a respective pair of terminal structures. The capacitor devices may have a relatively large capacitance value.
The first conductive layer may be a continuous conductive layer in which the plurality of first capacitor plates comprise integral portions thereof. The first conductive layer may define a common terminal structure as a further integral portion thereof.
Further objects of the present invention are achieved by an electronic device comprising at least one thin film capacitor arranged on a substrate. The capacitor of the electronic device has a capacitance of approximately equal to or greater than 14 nanofarad/mil
2
.
In some exemplary embodiments, the thin film capacitor is located between terminals configured for connection of the electronic device to external circuitry. The capacitor may have a dielectric layer with a thickness of no greater than approximately 1.0 &mgr;m. For example, the dielectric layer may have a thickness of approximately 0.8 to 1.0 &mgr;m. A PZT dielectric material applied by a sol-gel process may be utilized.
Other objects of the invention are achieved by a method of manufacturing a thin film capacitor array. As an initial step, the method involves providing a generally planar substrate. A first conductive layer is applied to the substrate and formed so as to define a plurality of first capacitor plates. A dielectric layer is then applied to cover the first capacitor plates of the first conductive layer. Next, a second conductive layer is applied to define a plurality of second capacitor plates opposed to respective of the first capacitor plates. An encapsulate material may also be applied over the layers on the substrate.
Other objects, features and aspects of the present invention are provided by various combinations and subcombinations of the disclosed elements, as well as methods of practicing same, which are discussed in greater detail below.
REFERENCES:
patent: 3268744 (1966-08-01), Kaiser et al.
patent: 3273033 (1966-09-01), Rossmeisl
patent: 3600652 (1971-08-01), Riley
patent: 3778689 (1973-12-01), Bodway
patent: 3821617 (1974-06-01), Shelby et al.
patent: 4251326 (1981-02-01), Arcidiacono et al.
patent: 4410867 (1983-10-01), Arcidiacono et al.
patent: 4439813 (1984-03-01), Dougherty et al.
patent: 4788524 (1988-11-01), Ozaki
patent: 4801469 (1989-01-01), Norwood
patent: 4933208 (1990-06-01), Dorinski
patent: 4971924 (1990-11-01), Tigelaar et al.
patent: 5065220 (1991-11-01), Paterson et al.
patent: 5079670 (1992-01-01), Tigelaar et al.
patent: 5108941 (1992-04-01), Paterson et al.
patent: 5206788 (1993-04-01), Larson et al.
patent: 5288660 (1994-02-01), Hua et al.
patent: 5370766 (1994-12-01), Desaigoudar et al.
patent: 5420745 (1995-05-01), Hidaka et al.
patent: 5450263 (1995-09-01), Desaigoudar et al.
patent: 5457598 (1995-10-01), Radford et al.
patent: 5466887 (1995-11-01), Hasegawa
patent: 5569880 (1996-10-01), Galvagni et al.
patent: 5600532 (1997-02-01), Michiya et al.
patent: 5625529 (1997-04-01), Lee et al.
patent: 5822175 (1998-10-01), Azuma
patent: 5880925 (1999-03-01), Dupre et al.
patent: 7-263277 (1995-10-01), None
U.S. application No. 09/293,817, Kennedy et al., filed Apr. 16, 1999.
Strandjord, Rogers, Ida, DeVellis, Shiau, Moyer, Scheck & Garrou, “Photosensitive Benzocyclobutene for Stress-Buffer and Passivation Applications (One Mask Manufacturing Process)”, in1997 Electronic Components and Technology Conference, 1997.
Liu and Mevissen, “Thick Layer Deposition of Lead P
AVX Corporation
Dinkins Anthony
Dority & Manning P.A.
LandOfFree
Ultra-small capacitor array does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Ultra-small capacitor array, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Ultra-small capacitor array will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2599895