Electrical connectors – Preformed panel circuit arrangement – e.g. – pcb – icm – dip,... – With provision to conduct electricity from panel circuit to...
Reexamination Certificate
1999-03-11
2001-02-06
Sircus, Brian (Department: 2839)
Electrical connectors
Preformed panel circuit arrangement, e.g., pcb, icm, dip,...
With provision to conduct electricity from panel circuit to...
C439S091000
Reexamination Certificate
active
06183267
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to ultra-miniature electrical contacts which are small enough and robust enough to make contact directly and reliably to micron size areas at any of numerous contact points on the face of an integrated circuit (IC), for example.
BACKGROUND OF THE INVENTION
As integrated circuits (ICs) become denser and denser with thousands and even millions of devices (e.g., memory cells, gates, etc.) on a single chip, the problem of making connections between external circuits and the devices on the chip becomes increasingly difficult. Frequently, a chip is encapsulated in a package with contacts on the chip permanently connected (e.g., by wire bonding, or otherwise), to relatively large external contacts on the package, such as the pins on a dual in-line package (DIP). Especially where the devices on an IC operate at speeds in the gigahertz (GH
z
) range, this method of connecting the internal devices on the chip to external circuits can cause impedance mismatching and imposes undesirable restraints on the overall speed of operation as well as significant added costs. It would therefore be highly desirable to be able to make connections directly to the devices on the chip with minimal physical separation from other devices, or from one chip to another.
Another widely used way to make connections to an IC is by means of solder “bumps” positioned in a pattern either on a substrate that matches the locations of the solder bumps to respective locations of small surface pads on the IC, or on the IC itself. The solder bumps are pressed against the pads and then reflowed thereby making permanent interconnections all at once. However, one disadvantage with this way of interconnection is that it results in a very rigid composite structure. The IC and substrate are held closely together with perhaps a thousand soldered joints. Unless the coefficients of thermal expansion of the IC and of the substrate are closely matched, differential expansion of the members when temperature changes during operation can cause rupture of an interconnection or fracture of the IC or substrate. It is highly desirable therefore that interconnections between an IC and a substrate be at least somewhat mechanically compliant. The present invention provides interconnections which while stable and low in resistance are also compliant.
From a cost standpoint, it would also be highly desirable in order to meet any particular or specific application to be able to assemble into an overall circuit individual off-the-shelf chips before they are sealed into separate packages. In order to do this to do this it must be possible to test the operation of the circuit and its individual chips before final packaging. Testing should be under conditions as nearly as possible equal to actual operating conditions. This also means as a practical matter that one or more individual ICs in the overall circuit, in the event the circuit does not operate properly for a particular application, should be easily replaceable even though the individual IC has met general specifications for itself alone.
In the past there have been various attempts to provide electrical contacts which meet the needs outlined above. Most if not all such attempts have been not entirely successful because of one or more shortcomings such as: not sufficiently small in size; or without adequate robustness to make stable electrical connections directly to contact pads on the face of an IC, or without adequate compliance to repeatedly make contact to surface pads without permanent deformation or “set”, or without ease of manufacturing and of assembly with the necessary high degrees of mechanical precision and electrical performance.
As is well known in the art of electrical connections, a prime requirement for an electrical contact is that it be able to make a stable and low resistance connection. To do this a contact should itself have high conductivity and enough physical strength (i.e., be robust enough) to exert adequate force against the member it is contacting. A contact should also act against the member to break through or scrape away any oxide (or high resistance film) on the surface between contact and member. These requirements for stability and low resistance are extremely difficult to meet when it is also necessary that the size of contacts be minute enough to make simultaneous electrical connections to a thousand or so micron-size contact pads (e.g., 80 or so microns square) on an IC.
The present invention provides ultra-miniature electrical contacts which are strong yet compliant, together with an efficient method of manufacturing and of precision assembly into electrical connectors, especially suitable for stable, low resistance temporary and/or permanent connections to the closely spaced area array and/or edge array contact pods of very dense ICs. The present invention is an important improvement upon that described in U.S. patent application, Ser. No. 08/942,623, filed Oct. 2, 1997, in the names of Robert B. Marcus and Yanwei Zhang. The disclosure in said patent application is referred to herein and is explicitly incorporated by reference into the present application.
SUMMARY OF THE INVENTION
In accordance with one aspect of the invention there are provided ultra-miniature electrical contacts having improved performance and versatility. The design of one such contact insures that when it is pressed down against a surface pad on an IC for example, the contact wipes against the pad and breaks through or scrapes away oxide or other high resistance film on the face of the pad. The contact is of high-conductivity material and has ample strength and resilience to bear against the pad with enough force to insure stable, low resistance electrical contact Each contact is initially formed on a substrate as a thin, narrow elongated flat body comprised of selectively deposited layers of metal. Depending on the final configuration desired for the contact, as illustrated hereinafter, the metal of a first metal layer has a first coefficient of thermal expansion (&agr;1), and the metal of another layer has a second thermal coefficient (&agr;2), which is different from &agr;1. Each contact is formed into a three-dimensional structure (as will be explained hereinafter) and is then made strong by a covering of a specialized metal plating which adds substantial stiffness and strength to the contact. This also makes the contact “springy” (compliant) and enables the contact to be deformed substantially without permanent deformation or “set”, a characteristic highly important to multiple electrical contacts making connections to a large number of surface pads on a chip or to the surface pads on many chips in a planar array. This is especially so when making repeated connections to one IC after another, as with a probe card for example.
Electrical contacts according to the invention are advantageously fabricated en masse on closely spaced and precisely located centers by photolithography, and selective deposition of metals and other materials through a series of process steps akin to ones employed in semiconductor manufacturing and which are well known. By way of example, ultra-miniature electrical contacts in accordance with the present invention are produced by: (a) providing a substrate, such as a silicon wafer, and depositing a thin insulating layer thereon, such as silicon nitride (Si
3
N
4
); (b) depositing a thin sacrificial layer, such as SiO
2
; (c) patterning the sacrificial layer using photolithography, so that strips of the sacrificial layer left after patterning define, at least roughly, the outline in planar form of each such electrical contact; (d) defining photographically the regions for metal deposition with photo resist thicker than the thickness of the metal to be deposited; (e) depositing (e.g., by sputtering) a layer of metal having a first coefficient of thermal expansion; (f) removing the resist along with unwanted metal; (g) depositing and patterning photoresist for a second layer of metal; (h) selectively depositi
Aharonov Robert Reuven
Kadija Igor V.
Marcus Robert B.
Brandeau Edward
Murray Hill Devices
Ostroff Irwin
Prasad Chandrika
Sircus Brian
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