Amplifiers – With semiconductor amplifying device – Including push-pull amplifier
Reexamination Certificate
2000-11-03
2001-07-03
Pascal, Robert (Department: 2817)
Amplifiers
With semiconductor amplifying device
Including push-pull amplifier
C330S292000
Reexamination Certificate
active
06255909
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to power amplifier circuits, and more particularly to an ultra low voltage CMOS, class AB power amplifier that uses inherent parasitic capacitance to accomplish internal compensation.
2. Description of the Prior Art
Numerous techniques are known for achieving class AB amplifiers with quiescent current control. These conventional techniques generally employ an input gain stage in front of a class AB output stage, and use well-known Miller capacitance techniques to compensate for the input gain stage in order to achieve the requisite amplifier stability.
One common technique to achieve stability for a class AB output stage uses a source-follower stage in parallel with the primary output MOSFET in order to provide a feed-forward zero and thereby assist the desired stability (compensation). Due to circuit complexity and component matching characteristics, these designs are not optimal.
In CMOS power amplifiers, the input gate capacitance, C
gs
, has been problematic due to its relatively large value (caused by its very large output device gate area). As requirements for driving lower and lower speaker impedance (32&OHgr;→4), and a reduced power supply environment (2.7V→1.5V), makes the output power FETs grow larger and larger, their parasitic capacitance, C
gs
, continues to grow. Recent developments in CMOS technology continue to grow this trend.
In view of the foregoing, a need exists for a CMOS power amplifier that has high drive capability in combination with lower quiescent current drain and more efficient use of available supply voltage than currently available using conventional CMOS class AB power amplifiers.
SUMMARY OF THE INVENTION
To meet the above and other objectives, the present invention provides an ultra low voltage CMOS class AB power amplifier architecture that uniquely uses the gate-source parasitic capacitance, C
gs
, of the primary output FETs as the main compensation capacitor. Since the CMOS class AB power amplifier output stage uses the output FET parasitic capacitance, C
gs
, as the main compensation capacitor, the amplifier very closely approximates a one pole system due to the inherent lack of a dominant parasitic capacitance, and the electrical properties of the load.
The class AB power amplifier can optionally include a quiescent current control circuit to reduce the quiescent current required, for example, in low distortion amplifiers. Any pole added to the system by the quiescent current control circuit must be kept quite small in relation to the power amplifier bandwidth. The present class AB amplifier output stage further provides high drive capability from low quiescent current while simultaneously achieving efficient utilization of available supply voltage.
According to one embodiment, a class AB power amplifier output stage employs CMOS output transistors having sufficiently large parasitic gate-source capacitance, C
gs
, such that the parasitic capacitance, C
gs
, can be used as a compensation capacitor to achieve power amplifier stability, especially in applications where the load impedance is sufficiently small.
According to another embodiment, a class AB power amplifier comprises: an input gain stage; and a PMOS output transistor having its source connected to a first supply voltage Vdd and having its gate driven by a PMOS driver transistor in response to a positive input signal generated via the input gain stage and further having a NMOS output transistor having its source connected to a second supply voltage Vss and further having its gate driven by a NMOS driver transistor in response to a negative input signal generated via the input gain stage, wherein the output transistors and the driver transistors are configured as a class AB output stage, and further wherein the PMOS output transistor and the NMOS output transistor are selected to have substantially identical and predetermined gate-source parasitic capacitance values, such that the gate-source parasitic capacitance of the PMOS output transistor and the gate-source parasitic capacitance of the NMOS output transistor combine to achieve a class AB power amplifier having a single dominant pole.
According to yet another embodiment, a power amplifier comprises: an input gain stage; and a class AB output stage having a pair of FET output power transistors, wherein each output power transistor is configured to have a sufficiently large current carrying capacity such that gate-source parasitic capacitance associated with the output power transistors can combine to achieve a desired level of internal gain compensation in response to a high frequency modulating signal generated via the input gain stage, and further wherein the power amplifier is devoid of Miller compensation.
According to still another embodiment, an amplifier circuit comprises: an input gain stage; and a class AB output stage devoid of Miller compensation and having a first output transistor and a second output transistor, wherein each output transistor has a transconductance parasitic capacitance configured to be responsive to positive and negative signals generated by the input gain stage such that the transconductance parasitic capacitances of the output transistors combine to achieve a desired unity gain frequency for the amplifier circuit.
In one aspect of the invention, a CMOS class AB amplifier output stage uses the parasitic gate-source capacitance, C
gs
, of the output transistors to achieve very high stability.
In another aspect of the invention, a CMOS class AB amplifier output stage use the parasitic gate-source capacitance, C
gs
, of the output transistors to achieve high drive capability in combination with lower quiescent current drain and more efficient use of available supply voltage than currently available using conventional class AB line driver output stages.
In yet another aspect of the invention, a CMOS class AB power amplifier output stage uses the parasitic gate-source capacitance, C
gs
, of the output transistors to reduce the physical size of the amplifier.
In still another aspect of the invention, a CMOS class AB power amplifier architecture is implemented to substantially eliminate unwanted effects of parasitic capacitance associated with the output transistors.
REFERENCES:
patent: 4959623 (1990-09-01), Khoury
patent: 4963837 (1990-10-01), Dedic
patent: 5162753 (1992-11-01), Khorramabadi
patent: 5936468 (1999-08-01), Wiese et al.
Patent Application No. 09/491,543, filed Jan. 26, 2000, Docket No. TI-28148, “A Distortion Correction Loop For Amplifier Circuits” (John Muza).
Brady III Wade James
Choe Henry
Holmbo Dwight N.
Pascal Robert
Telecky , Jr. Frederick J.
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