Ultra low power pumped n-channel output buffer with self-bootstr

Details Ultra low power pumped n-channel output buffer with self-bootstr Ultra low power pumped n-channel output buffer with self-bootstr

1996-09-30

1998-10-27

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Gating

Signal transmission integrity or spurious noise override

327434, 327589, H03K 1716

Patent

active

058282629

ABSTRACT:
An ultra-low power pumped n-channel transistor output buffer with self-bootstrapping includes an n-channel pullup transistor as the primary pullup device. A gate-to-source capacitance C.sub.gs of the pullup transistor is used to self-bootstrap the input data signal. A pass n-channel transistor is connected between the input data signal, and the gate of the pullup transistor, and is biased on a gate terminal thereof by a charge pump having a voltage magnitude one device threshold higher than the device operating rail V.sub.cc. The pass transistor, so biased, permits the input data signal, which may have a magnitude of V.sub.cc, to charge C.sub.gs. An over-voltage can be developed on the gate of the pullup transistor by the self-bootstrapping effect of C.sub.gs. The pass transistor, in addition, so biased, prevents such over-voltage on the pullup transistors gate from being shorted to V.sub.cc through a driving device. The output buffer also includes a p-channel transistor having source and drain terminals defining a channel that is connected between another pumped voltage rail, and the gate of the pullup transistor. This p-channel transistor is activated when the output on the pad is desired to be a logic one, and operates to replenish any charge lost on the bootstrap capacitance due to leakage on the gate of the pullup transistor, or from leakage on the drain of the pass transistor. A second capacitor, similar in size to the pass transistor capacitance, is connected between the gate of the pass transistor, and the gate of a pulldown n-channel transistor, and operates to equalize and reduce the effect of transition changes in the input data signal.

REFERENCES:
patent: 4042838 (1977-08-01), Street et al.
patent: 4219743 (1980-08-01), Millns et al.
patent: 4484092 (1984-11-01), Campbell, Jr.
patent: 4503343 (1985-03-01), Ohuchi
patent: 4540898 (1985-09-01), Pumo et al.
patent: 4574273 (1986-03-01), Atsumi et al.
patent: 4612462 (1986-09-01), Asano et al.
patent: 4725746 (1988-02-01), Segawa et al.
patent: 5216290 (1993-06-01), Childers
patent: 5241502 (1993-08-01), Lee et al.
patent: 5270588 (1993-12-01), Choi
patent: 5281869 (1994-01-01), Lundberg
patent: 5381061 (1995-01-01), Davis
patent: 5399920 (1995-03-01), Van Tran
patent: 5656571 (1997-08-01), Ohashi
"MOSFET Powering Circuit", Sonoda, G., IBM Technical Disclosure Bulletin, vol. 13, No. 9, pp. 2658, Feb. 1971.
"Bootstrap Inverter Driver," Harroun, V.T., IBM Technical Disclosure Bulletin, vol. 19, No. 3, pp. 827-28, Aug. 1976.
"Bufferized ECL-Type Logic Circuit," IBM Technical Disclosure Bulletin, vol. 33, No. 4, pp. 343-344, Sep. 1990.

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