Ultra low power adder with sum synchronization

Details Ultra low power adder with sum synchronization Ultra low power adder with sum synchronization

2006-01-24

2006-01-24

Ingberg, Todd (Department: 2193)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

C708S706000

Reexamination Certificate

active

06990509

ABSTRACT:
An ultra low power adder with sum synchronization which provides a power reduction method in the binary carry propagate adders by using a carry skip technique. The invention eliminates glitches at the adder outputs by preventing signal transitions at the sum outputs until the corresponding carry signals have reached their final values, which is achieved by adding a synchronization circuitry to the sum calculation path.

REFERENCES:
patent: 3553446 (1971-01-01), Kruy
patent: 4623982 (1986-11-01), Ware
patent: 4683548 (1987-07-01), Mlynek
patent: 4885716 (1989-12-01), Little
patent: 4982352 (1991-01-01), Taylor et al.
patent: 5631860 (1997-05-01), Morinaka
patent: 5636157 (1997-06-01), Hesson et al.
patent: 5838602 (1998-11-01), Feiller et al.
patent: 6188240 (2001-02-01), Nakaya
patent: 6829729 (2004-12-01), Hicks et al.

Affiliated with

Also associated with

Rating

Ultra low power adder with sum synchronization does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Ultra low power adder with sum synchronization, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Ultra low power adder with sum synchronization will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3553825