Ultra low pin count interface for die testing

Details Ultra low pin count interface for die testing Ultra low pin count interface for die testing

2008-07-29

2008-07-29

Tang, Minh N. (Department: 2829)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

C324S763010, C714S734000

Reexamination Certificate

active

11385131

ABSTRACT:
An apparatus, a method and a system to test a device. An input/output (I/O) block communicates with an external tester to receive test data and to send test result using first and second communication modes. A logic block parses the test data. A memory stores microcode from the parsed test data. The microcode contains a test program to test a circuit. A controller executes the test program.

REFERENCES:
patent: 5805605 (1998-09-01), Lee et al.
patent: 6286115 (2001-09-01), Stubbs
patent: 6551844 (2003-04-01), Eldridge et al.
patent: 7259582 (2007-08-01), Ong
patent: 2002/0158271 (2002-10-01), Kouchi et al.
patent: 1019980012169 (1998-04-01), None
International Search Report and Written Opinion of the International Searching Authority Dated Aug. 16, 2007, International Application No. PCT/US2007/064306.

Affiliated with

Also associated with

Rating

Ultra low pin count interface for die testing does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Ultra low pin count interface for die testing, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Ultra low pin count interface for die testing will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3917383