Oscillators – Automatic frequency stabilization using a phase or frequency... – With reference oscillator or source
Reexamination Certificate
2001-05-25
2004-02-03
Pascal, Robert (Department: 2817)
Oscillators
Automatic frequency stabilization using a phase or frequency...
With reference oscillator or source
C331S025000, C331S045000, C331S074000
Reexamination Certificate
active
06686805
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to a clocking system, and more particularly, to a device and method that reduce jitter and generate clock signals.
BACKGROUND
Read, write, and servo channels used in hard drives can require three different clock sources. A read and write head can require separate clock signals to transform electrical signals into magnetic signals and magnetic signals into electrical signals, respectively. A servo can require a separate clock signal to accurately position a head on or above a surface of a hard drive platter. In each of these systems, the clock pulses are very high frequency clock pulses.
Clock management of read, write, and servo channels can be handled by multiple clock synthesizers that have a programmable output frequency over a wide bandwidth. One operational concern of some multiple clock synthesizers is the large amount of power these synthesizers can consume when distributing timing pulses. Multiple clock synthesizers having a large programmable frequency bandwidth can use multiple pairs of transistors that require high voltage biases to achieve high operating frequencies. Moreover, some oscillators contained within clock synthesizers can introduce and accumulate phase error. The phase error can degrade the performance of some clock synthesizers.
REFERENCES:
patent: 5668504 (1997-09-01), Rodriques Ramalho
patent: 5877657 (1999-03-01), Yoshinaka
patent: 5920596 (1999-07-01), Pan et al.
patent: 6111712 (2000-08-01), Vishakhadatta et al.
patent: 6137336 (2000-10-01), Baba et al.
patent: 6288589 (2001-09-01), Potter et al.
“Synchronous Recording Channels—PRML & Beyond”, rev. 5.61 14.E.18, 1999, published by Knowledge Tek, Inc., Broomfield, Colorado.
PRML: Seagate Used Space Age Technology Today, available at http://www.seagate.com/support/kb/disc/prml.html (2001), printed on Apr. 9, 2001, 2 pages.
Industry Technologies—PRML, Technologies Storage, availabe at http://wwww.idema.org/about/industry/ind tech prml.html (2001), printed on Apr. 9, 2001, 1 page.
Kozierok, Charles M., Hard Disk Data Encoding and Decoding, available at http://www.storagereview.com/guide2000/ref/hdd/geom/data.html (2001), printed on Apr. 9, 2001, 2 pages.
Kozierok, Charles, M., Technical Requirements for Encoding and Decoding, available at http://www.storagereview.com/guide 2000/ref/hdd/geom/dataRequirements.html (2000), printed on Apr. 9, 2001, 3 pages.
Kozierok, Charles M., Run Length Limited (RLL), available at http://www.storagereview.com/guide2000/ref/hdd/geom/dataRRLL.html (2000), printed on Apr. 9, 2001, 3 pages.
Kozierok, Charles M., Partial Response, Maximum Likelihood (PRML), available at http://www.storagereview.com/guide2000/ref/hdd/geom/dataPRML.html (2000), printed on Apr. 9, 2001, 3 pages.
Kozierok, Charles M., Extended PRML (EPRML), available at http://www.storagereview.com/guide2000/ref/hdd/geom/dataEPRML.html (2000), printed on Apr. 9, 2001, 2 pages.
MR and PRML: Technologies in Synergy, available at http://www.lionsgate.com/Home/baden/public_html_index/SCSI/Quantum_White_Papers/MR_Head/MR (1996), printed on Apr. 9, 2001, 4 pages.
Western Digital Corporation—Glossary of term Viterbi Detection, available at http://www.westerndigital.com/company/glossary.html (2001), printed on Apr. 9, 2001, 1 page.
Fleming, Chip, A Tutorial on convolutional Coding with Viterbi Decoding, available at http://pwl.netcom.com/~chip.f/viterbi/tutorial.html (2001), printed on Apr. 9, 2001, 4 pages.
Fleming, Chip, A Tutorial on Convolutional Coding with Viterbi Decoding—Description of the Data Generation, Co. . . . v, available at http://pwl.netcom.com/~chip.f/viterbi/algrthms.html (2001), printed on Apr. 9, 2001, 6 pages.
Using the Virtex Delay-Locked Loop, Advanced Application Note, XAPP 132, Oct. 21, 1998 (Version 1.31) 14 pages.
Telecommunications Dictionary, available at http://www.ctechsolutions.com/dictionary.htm, (2002), printed Sep. 9, 2002, p. 44.
Using the Virtex Delay-Locked Loop, XAPP 132, Jul. 11, 2002 (Version 2.5), printed Aug. 30, 2002, 11 pages.
Brinks Hofer Gilson & Lione
Glenn Kimberly E
Pascal Robert
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