Ultra high-speed Nor-type LSDL/Domino combined address decoder

Details Ultra high-speed Nor-type LSDL/Domino combined address decoder Ultra high-speed Nor-type LSDL/Domino combined address decoder

2008-03-25

2008-03-25

Phung, Anh (Department: 2824)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S230080

Reexamination Certificate

active

11538877

ABSTRACT:
An ultra high speed address decoder uses a combination of Domino logic circuits and LSDL logic circuits. N address bits are converted into N logic true address bits and N complementary address bits. A partial address decoder generates two bit groups using selected of the N logic true address bits and N complementary address bits in NOR logic structures such only two cascaded NFETS are used in a logic tree. The bit groups are partitioned to optimize the layout of the parallel bit lines in the address decoder.

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