Ultra high speed heterojunction bipolar transistor having a...

Active solid-state devices (e.g. – transistors – solid-state diode – Heterojunction device

Reexamination Certificate

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C257S018000, C257S197000, C257S198000, C257S627000, C257S628000

Reexamination Certificate

active

06680494

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to improvements in heterojunction bipolar transistors (“HBT”) and, more particularly, to a practical HBT construction that obtains both an improved figure of merit in HBT performance and an improved maximum frequency of oscillation for the HBT.
BACKGROUND
Heterojunction bipolar transistors (“HBT”), which find application, as example, in high speed (eg. high frequency) digital switching, are known and well defined in the technical literature. The HBT is a layered structure, such as illustrated in side view (width) in FIG.
1
. That layered structure includes a semiconductor substrate
1
, a subcollector
3
, collector
5
, base
7
and emitter
9
stacked one atop the other in an integral assembly. Metal contacts are formed on the emitter, base and subcollector for appropriate connection to external power supply and/or other electronic circuits. Those metal contacts include a subcollector metal
11
, a base metal
13
, and emitter metal
15
.
In top view the familiar HBT appears as in
FIG. 2
, wherein the subcollector
3
defines a large rectangle in shape. Within that rectangular region and, as viewed from the top, the rectangular shaped emitter metal
15
is formed atop and almost covers the rectangular region of the emitter layer
9
, also rectangular in shape. The base metal
13
is formed upon the base layer
7
and essentially forms a picture-frame like structure surrounding emitter layer
9
. The outer dimensions of base metal
13
fall short of the rectangular area defined by the base layer
7
, the length, l, and width, w, of which, is referred to as the base mesa length and base mesa width. Collector
5
directly underlies base
7
and is not visible in this view. The collector metal
11
that is formed on subcollector layer
3
is an elongate rectangle in shape. It is noted that substrate
1
is omitted in this view.
A common HBT is the Indium Aluminum Arsenide, Indium Gallium Arsenide & Indium Phosphide (“InAlAs/InGaAs/InP”) HBT, and the invention is more easily understood with that type of HBT as the example. Such HBT transistors are grown on an epi-layer of InP material, a crystalline wafer that is sliced from a large crystal (the boule) that is grown from a “seed.” Typically the wafer is supplied by a specialty manufacturer, the crystal grower, to the transistor manufacturer and that wafer contains straight edges along two sides of the wafer. Those two straight edges are perpendicular to one another. Each straight edge is aligned with (formed parallel to) a respective plane of the crystal of the wafer as an aid to mask alignment for the photo-lithographic procedures used during manufacture of the HBT. Using conventional crystal growing techniques (such as molecular beam epitaxy, MBE) the additional layers necessary to form the transistor are grown on the face of the crystalline InP wafer, effectively further growing the crystal structure of the wafer in height.
The first additional layer, subcollector
3
, is formed of a layer of InGaAs over a layer of InP material that has been doped negative, that is, the InGaAs and InP contains an impurity, typically Silicon, which gives the semiconductor layer a low electrical resistivity. The low resistivity enables the layer to serve as an electrical conductor to provide an electrical path from the collector metal
11
to the underside of collector
5
. The next layer, the collector of the HBT, is grown using InP material, which is doped negative, but at a lower concentration than the doping of the subcollector. The collector is followed by growing a layer of InGaAs, the base
7
of the HBT, which is doped heavily positive using an impurity, customarily of Beryllium. The final semiconductor layer, the emitter
9
, is grown of InAlAs (Indium Aluminum Arsenide) that is medium doped negative with Silicon.
Once the laminate-like crystal structure is completed, the masking and etching procedures follow to define the shape and size of the various layers, such as was illustrated in FIG.
2
. The InAlAs/InGaAs/InP wafer structure is first masked and then etched with a phosphoric acid based solution that etches the top InAlAs layer. Then the structure is masked again and the InGaAs base layer is etched. Then the structure is masked and then etched with a hydrochloric (“HCl”) acid based solution that etches the InP. For greater detail of the known processes, the reader is referred to the technical literature.
The available space (“real estate”) on the wafer is sufficient to accommodate perhaps thousands of HBT's. Thus the mask contains the individual masks of identical layer geometry arranged in rows and columns to permit simultaneous fabrication of large numbers of HBT's and circuits containing HBTs. Those HBT's may later be cleaved (“diced”) from the wafer and separated for individual packaging or retained on the substrate for use in a semiconductor array. For an understanding of the present invention only an individual HBT structure needs to be considered.
Once etching is completed, metal contacts are deposited in place on the subcollector, base and emitter layers. Typically a layer of a dielectric or polyimide, a plastic insulator, is used to cover the semiconductor, except for the regions on which the metal contacts are to be deposited. After deposition of the contact metal the conductive leads to the metal are deposited on and extend over that dielectric or polyimide insulator layer.
In the InAlAs/InGaAs/InP HBT of
FIG. 1
, as example, substrate
1
is about 500-600 microns in thickness, the subcollector
3
about 4,000 Angstroms ({fraction (1/10,000)}
th
micron) thick, the collector
5
about 4,000 Angstroms thick, base
7
about 400 Angstroms and emitter
9
about 2,500 Angstroms in thickness. The metal contacts are about 2000 Angstroms in thickness. The foregoing dimensions illustrate the relative thickness (or scale) of the various regions of the HBT.
The function of the elements of the HBT and its theory of operation are well documented in the technical literature, and is not here repeated. Basically with the base, emitter and collector properly electrically biased, the HBT serves as an electronic switch or amplifier. As example, that electronic switch conducts current or not between emitter and collector in dependence on the application of a voltage of appropriate level to the base.
Being used in high speed digital application, the higher the operating frequency at which the device operates and the higher the figure of merit of a given HBT design, the better. The design consideration for each of those two factors are different and contradictory. It is found that enhancing the one factor is disparaging of the other factor and vice-versa.
As study has shown, the most important figures of merit of high frequency performance heterojunction bipolar transistors (HBT) are f
max
and f
&tgr;
. where f
max
is the frequency at which unilateral gain becomes unity and f
&tgr;
is the current-gain cutoff frequency. An approximate expression of f
max
is (1)
f
max
=
f
τ
8

π



R
B

C
BC
,
where R
B
is the parasitic base resistance and C
BC
is the base collector capacitance. Equation (1) shows the relation of f
max
to f
&tgr;
, R
B
and C
BC
. To enhance f
max
, f
&tgr;
should be increased and R
B
and C
BC
should be minimized.
R
B
is the parasitic base resistance, which is essentially a combination of the ohmic contact resistance and the base access resistance of the transistor.
FIG. 3
is a simplified diagram that shows those two resistive components. The base contact resistance is dependent upon the base layer material, the base layer doping and the ohmic metal technology used to fabricate the base contact, which are nearly independent of the base layer thickness. On the other hand, the base access resistance is inversely proportional to base layer thickness. For a given material and doping, thick base layers provide low base access resistance, while thin base layers possess high access resistance. Consequently, to reduce R
B
, the

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